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mixed-signal front-end (mxfe ? ) baseband transceiver for broadband applications AD9861 rev. 0 in fo rmation furn ished by an alog d e v i c e s is believed to be accurate and reliable. how e ver, n o resp on sibili ty is assume d b y a n alog de vices fo r its use, nor for an y i n fri n geme nt s of p a t e nt s or ot h e r ri ght s o f th ird parties th at may result fro m its use . s p ecificatio n s subj ec t to ch an g e witho u t n o tice. no licen s e is g r an te d by implicati o n or ot herwi s e u n der a n y p a t e nt or p a t e nt ri ghts of analog de v i ces. trademarks an d registered tra d ema r ks are the prop erty o f their respective ow ners. one technolog y way, p.o . box 9106, norwood, ma 02062-9106, u.s.a. t e l: 781. 329. 4 700 www.analog.com fax: 781. 326. 87 03 ? 2003 analog de vices, i n c. al l r i ght s r e ser v ed . feature s receive path in cludes dua l 10 - b it analog-to-d i gital converters with internal or ex ternal refer e nce, 50 msps and 80 msps versions transmit path i n cludes dual 1 0 -bit, 200 msp s digital-to- analog converters with 1, 2, or 4 interpol ation and programmable gain control internal clock distribution block includes a programmable phase-locked l oop and timing generation circuitry, allowing single-reference clock operation 20-pin flexible i/o data interfa c e allows vario u s interl eave d or noninterleaved data transf ers in half -dupl e x mode and interleaved dat a transfers in f u ll- duplex mod e configurable t h rough register programmabi lity or optionally limi ted programmability through mode pins independent r x and tx power - down control pins 64-lea d lfcsp package (9 mm 9 mm footprint) 3 configurable auxiliar y conve r ter pins application s b r o a dband access b r o a dband lan communications (modems) functional block diagram data mux and latch data latch and demux i/o interface configuration block AD9861 i/o interface control flexible i/o bus [0:19] rx data tx data adc vin+a vin ? a adc vin+b vin ? b low-pass interpolation filter dac iout+ a iout? a dac iout+b iout? b aux adc aux dac aux dac aux dac aux adc clkin adc clock 03606-0-001 dac clock pll fi g u r e 1 . general description the AD9861 is a mem b er o f the mxfe fa mil y a g r o u p o f i n t e gra t ed co n v e r t e r s f o r th e co m m un ica t i o n s m a r k et . th e AD9861 in t e g r a t es d u al 10-b i t analog-t o-dig i tal co n v er t e rs (ad c ) an d d u a l 10-b i t dig i t a l - to -a na lo g co n v er ters (tx d a c ?). t w o sp ee d g r ades a r e a v a i la b l e , -50 a nd -80. the -50 is o p ti- mi ze d fo r a d c s a m p ling o f 50 ms ps an d less, w h i l e t h e -80 is o p tim i ze d fo r ad c s a m p le ra t e s bet w een 5 0 ms p s and 80 ms ps. the du al txdacs operate at sp eeds up to 200 mhz and inclu d e a by pas s able 2 or 4 i n terpolat ion fi lt er. thre e auxili ary conve r ters are also a v aila ble to provi d e require d system le vel co ntrol voltag es or to monitor sys t em s i gnals. th e AD9861 is optimized for high pe rformance, lo w power, small form factor, and to provide a c o st-effective solution for the br o a db a nd co m m un ica t io n ma r k et. the AD9861 us es a sin g le in p u t c l o c k p i n (clkin) t o g e nera te al l sys t em clo c ks. the adc and txdac cloc ks are generat e d w i t h in a tim i n g ge ne ra ti on b l ock tha t prov id es use r program m a - bl e op t i o n s su c h as div i de c i rc uit s , pl l mu lt ip lie r s, and switc h es. a flexible, bidir e ctional 20-bit i / o bus accommodate s a v a riety of custom d i gital back e n d s or open market dsps. in half-duplex s y stems, the in terface supports 20-bit parallel transfers or 10-bit interleaved tran sfers. i n full-duplex syste m s, the i n t e rface su pports an inte rl eave d 10- bit a d c bus and an int e rleav e d 10 - b it txda c bus. the fl exibl e i/ o bus reduc e s p i n count and, ther efore, reduces t h e require d pac kage s i ze on t h e AD9861 and the device to whic h it connec ts. the AD9861 c a n use either mo de pins or a serial program- mable i n terf ace (spi) to configur e the i n t e rface bus, operate the adc i n a lo w p o wer mode , con f igure th e txd a c i n terpola t io n r a te, a n d co ntr o l adc a n d tx d a c po wer - do w n . t h e s p i provid es m o re programmab l e opti on s for b o th th e t x d a c p a t h (fo r ex ample, c o ar se an d fi ne g a i n co ntr o l a nd o ffset co ntr o l fo r channel matchi ng) and t h e ad c pat h (for example, t h e i n t e rnal duty cy cle sta b il izer, a n d twos c o mplem e n t d a t a format). the AD9861 is packaged in a 6 4 -lead lfcsp (l ow profile, fine pitche d, c h ip sc ale pac kag e). the 64-le ad lfc s p footprint is o n ly 9 mm 9 mm, an d i s less tha n 0.9 mm hi gh, fit t i n g i n to tigh tly space d a pplicat ions suc h as pc mcia c a rds
AD9861 rev. 0 | page 2 of 52 table of contents tx path specifications ...................................................................... 3 rx path specifications ...................................................................... 4 power specifications ......................................................................... 5 digital specifications ........................................................................ 5 timing specifications ....................................................................... 6 absolute maximum ratings ............................................................ 7 esd caution .................................................................................. 7 pin configuration and pin function descriptions ...................... 8 typical performance characteristics ........................................... 10 te r m i no l o g y .................................................................................... 21 theory of operation ...................................................................... 22 system block ............................................................................... 22 rx path block .............................................................................. 22 tx path block .............................................................................. 24 auxiliary converters .................................................................. 27 digital block ................................................................................ 30 programmable registers ............................................................ 42 clock distribution block .......................................................... 45 outline dimensions ....................................................................... 49 ordering guide .......................................................................... 50 revision history revision 0: initial version
AD9861 rev. 0 | page 3 of 5 2 tx path specifications table 1. ad98 61-50 a nd a d 9 861-80 f dac = 2 00 ms ps; 4 i n terpol ation; r set = 4 . 02 k?; differential lo ad resista n ce of 100 ? 1 ; txpga = 20 db, avdd = dvdd = 3.3 v, unles s ot herwi s e not e d p a r a m e t e r t e m p t e s t leve l m i n t y p m a x u n i t tx path gene r al r e s o l u t i o n f u l l i v 1 0 b i t s maximum dac update rate full iv 200 mhz maximum full-s c ale output current full iv 20 ma full-scale error full v 1% gain mismatch error 25c iv C3.5 +3.5 % fs offset mismatch error full iv C0.1 +0.1 % fs reference voltage full v 1.23 v output capacitance full v 5 pf phase noise (1 khz offset, 6 mh z tone) 25c v C115 dbc/hz output voltage compli ance ran g e full iv C1.0 +1.0 v txpga gain range full v 20 db txpga step size full v 0.10 db tx path dyna mic perfor m a n ce (i ou t f s = 20 ma; f ou t = 1 m h z) s n r f u l l i v 6 0 . 2 6 0 . 8 d b s i n a d f u l l i v 5 9 . 7 6 0 . 7 d b t h d f u l l i v ? 7 7 . 5 ? 6 5 . 8 d b c sfdr, wideband (dc to nyquist) full iv 64.6 76.0 dbc sfdr, narrowband (1 mhz window) full iv 72.5 81.0 dbc 1 see figure 2 for description of the tx dac termination sc heme. 03606-0-030 txdac 50 ? 50 ? f i g u re 2. d i ag r a m sho w ing t e r m i n at i o n of 1 0 0 ? d i f f e r e nt ia l l oad f o r s o me t x da c m e as u r e m ent s
AD9861 rev. 0 | page 4 of 52 rx path specifications table 2. AD9861-50 and AD9861-80 f adc = 50 msps for the AD9861-50, 80 msps for the AD9861-80; internal reference; differential analog inputs, adc_avdd = dvdd = 3.3v , unless otherwise noted parameter temp test level min typ max unit rx path general resolution full v 10 bits maximum adc sample rate full iv 50/80 msps gain mismatch error full v 0.2 % fs offset mismatch error full v 0.1 % fs reference voltage full v 1.0 v reference voltage (reftCrefb) error full iv C30 6 +30 mv input resistance (differential) full v 2 k? input capacitance full v 5 pf input bandwidth full v 30 mhz differential analog input voltage range full v 2 v p-p differential rx path dc accuracy integral nonlinearity (inl) 25c v 0.75 lsb differential nonlinearity (dnl) 25c v 0.75 lsb aperature delay 25c v 2.0 ns aperature uncertainty (jitter) 25c v 1.2 ps rms input referred noise 25c v 450 uv AD9861-50 rx path dynamic performance (v in = C0.5 dbfs; f in = 10 mhz) snr full iv 55.5 60 dbc sinad full iv 55.6 60 dbc sinad 25c iv 58.5 60 dbc thd (second to ninth harmonics) full iv ?71.5 ?64.6 dbc sfdr, wideband (dc to nyquist) full iv 65.7 73.5 dbc crosstalk between adc inputs full v 80 db AD9861-80 rx path dynamic performance (v in = C0.5 dbfs; f in = 10 mhz) snr full iv 55.4 59.5 dbc sinad full iv 52.7 59.0 dbc thd (second to ninth harmonics) full iv ?67 dbc sfdr, wideband (dc to nyquist) full iv 67 dbc crosstalk between adc inputs full v 80 db
AD9861 rev. 0 | page 5 of 52 power specifications table 3. AD9861-50 and AD9861-80 analog and digital supplies = 3.3 v; f clkin = 50 mhz; pll 4 setting; normal timing mode parameter temp test level min typ max unit power supply range analog supply voltage (avdd) full iv 2.7 3.6 v digital supply voltage (dvdd) full iv 2.7 3.6 v driver supply voltage (drvdd) full iv 2.7 3.6 v analog supply currents txpath (20 ma full-scale outputs) full v 70 ma txpath (2 ma full-scale outputs) full v 20 ma rx path (-80, at 80 msps) full v 165 ma rxpath (-80, at 40 msps, low power mode) full v 82 ma rxpath (-80, at 20 msps, ultral ow power mode) full v 35 ma rx path (-50, at 50 msps) full v 103 ma rxpath (-50, at 50 msps, low power mode) full v 69 ma rxpath (-50, at 16 msps, ultral ow power mode) full v 28 ma txpath, power-down mode full v 2 ma rxpath, power-down mode full v 5 ma pll full v 12 ma digital supply currents txpath, 1 interpolation, 50 msps dac update for both dacs, half-duplex 24 mode full v 20 ma txpath, 2 interpolation, 100 msps dac update for both dacs, half-duplex 24 mode full v 50 ma txpath, 4 interpolation, 200 msps dac update for both dacs, half-duplex 24 mode full v 80 ma rxpath digital, half-duplex 24 mode full v 15 ma digital specifications table 4. AD9861-50 and AD9861-80 parameter temp test level min typ max unit logic levels input logic high voltage, v ih full iv drvdd C 0.7 v input logic low voltage, v il full iv 0.4 v output logic high voltage, v oh (1 ma load) full iv drvdd C 0.6 v output logic low voltage, v ol (1 ma load) full iv 0.4 v digital pin input leakage current full iv 12 a input capacitance full iv 3 pf minimum reset low pulse width full iv 5 input clock cycles digital output rise/fall time full iv 2.8 4 ns
AD9861 rev. 0 | page 6 of 52 timing specifications table 5. AD9861-50 and AD9861-80 parameter temp test level min typ max unit input clock clkin clock rate (pll bypassed) full iv 1 200 mhz pll input frequency full iv 16 200 mhz pll ouput frequency full iv 32 350 mhz txpath data setup time (hd20 mode, time re quired before data latching edge) full v 5 ns (see clock distribution block section) hold time (hd20 mode, time required after data latching edge) full v C1.5 ns (see clock distribution block section) latency 1 interpolation (data in until peak output response) full v 7 dac clock cycles latency 2 interpolation (data in until peak output response) full v 35 dac clock cycles latency 4 interpolation (data in until peak output response) full v 83 dac clock cycles rxpath data output delay (hd20 mode, t od ) full v C1.5 ns (see clock distribution block section) latency full v 5 adc clock cycles table 6. explanation of test levels level description i 100% production tested. ii 100% production tested at 25 c and guaranteed by design and characterization at specified temperatures. iii sample tested only. iv parameter is guaranteed by desi gn and characterization testing. v parameter is a typical value only. vi 100% production tested at 25 c and guaranteed by design and characteri zation for industrial temperature range.
AD9861 rev. 0 | page 7 of 5 2 absolute maximum ratings table 7. p a r a m e t e r r a t i n g electrical avdd voltage 3.9 v max drvdd voltage 3.9 v max analog input voltage C0.3 v to av dd + 0.3 v digital input voltage C0.3 v to dv dd C 0.3 v digital output c u rrent 5 ma max environmenta l operating tem p erature range (ambient) C40 c to +85 c maximum junction temperature 150 c lead t e m p e r atu r e (s o l der i n g , 1 0 se c) 300 c storage temperature range (ambient) C65 c to +150 c s t r e s s es a b o v e t h os e lis t e d u n de r t h e a b s o l u t e m a xim u m r a tin g s m a y ca use pe rm a n en t d a ma g e t o t h e devi ce . t h is i s a st re ss r a t i n g on l y ; f u nc t i on a l op e r a t i o n of t h e d e v i c e a t t h e s e or a n y o t h e r con d i t io n s ab o v e t h o s e i n di ca t e d in t h e op era t io nal s e c t io n o f t h is sp e c if ic a t io n is no t im plie d . e x p o sur e t o a b s o l u te max i m u m ra t i ng co ndi t i on s fo r ex ten d e d p e r i o d s ma y a f fe c t de vice r e l i ab i l i t y . ther ma l resi stanc e 64-lead lfcs p (4-la y er bo a r d): ja = 24.2 (p addle s o lder ed t o g r o u n d p l a n , 0 lpm air) ja = 30.8 (p addle n o t s o lder e d t o g r o u nd p l an, 0 lpm air) esd caution esd (electrostatic discharge) sensitive device. ele c trosta tic charg e s as high as 4000 v readily accumulate on the human body and test eq uipment and can discharge with out detection. although this product features proprietary esd protection circu i try, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. theref ore, prop er esd precautions a r e recommended to avoid perform a nce degradation or l o ss of functiona l ity.
AD9861 rev. 0 | page 8 of 5 2 pin conf iguration and pi n function descriptions 03606-0-019 iface 2 17 iface 3 18 u9 19 u8 20 u7 21 u6 22 u5 23 u4 24 u3 25 u2 26 u1 27 u0 28 aux _ daca/aux _ adca2 29 aux _ dacb/aux _ adca1 30 drv dd 31 d r vss 32 spi_c s 64 tx p w rdwn 63 rx p w rdwn 62 adc_ av dd 61 re ft 60 adc_ av s s 59 vin + a 58 vin ? a 57 vr ef 56 vin ? b 55 vin + b 54 adc_ av s s 53 re fb 52 adc_ av dd 51 p ll_ av dd 50 pll_a vss 49 spi_dio 1 spi_clk 2 spi_sdo/aux_spi_sdo 3 adc_lo_pwr/aux_spi_cs 4 dvdd 5 dvss 6 avdd 7 iout?a 8 iout+a 9 agnd 10 refio 11 fsadj 12 agnd 13 iout+b 14 iout?b 15 avdd 16 clkin 48 auxadc_ref 47 reset 46 aux_dacc/aux_adcb 45 l0 44 l1 43 l2 42 l3 41 l4 40 l5 39 l6 38 l7 37 l8 36 l9 35 aux_spi_clk 34 iface1 33 AD9861 top view (not to scale) f i gure 3. pin config ur ation ta ble 8. pi n f u nct i on d e s c ri pt i o ns pin no . name 1 description 2, 3 1 s p i _ d i o ( interp1 ) spi: serial port data input. no spi: tx interpolation pin, msb. 2 s p i _ c l k ( interp0 ) spi: serial port shift clock. no spi: tx interpolation pin, lsb. 3 s p i _ s d o / a u x s p i _ s d o ( fd/ hd ) spi: 4-wire serial port data outp ut/ data output pin for aux s pi. no spi: configures full-duple x or half-duplex m o d e . 4 adc_lo_pwr/aux_spi_cs adc low power mode en able. defined at power-up. cs for auxs pi. 5, 31 dvdd digital supply. 6, 32 dvss digital ground. 7, 16, 50, 51, 61 avdd analog supply. 8, 9 ioutCa, iout+a dac a differential output. 10, 13, 49, 53, 59 agnd, avs s analog ground. 11 refio tx dac band gap reference decoupling pin. 12 fsadj tx dac full-scale adjust pin. 14, 15 iout+b, iout?b dac b differenti a l output. spi : buffered cl kin. can be conf igured as system clock output. 1 7 i f a c e 2 ( 10/ 20 ) no spi : for fd : buffered clkin; for hd20 or hd 10 : 10/ 20 configuration pin. 1 8 i f a c e 3 c l o c k o u t p u t . 19C28 u9Cu0 upper data bit 9 to upper data bit 0. 29 aux1 configurable as either auxadc_a2 or auxdac_ a . 30 aux2 configurable as either auxadc_a1 or auxdac_ b . spi : for fd : txsync; for hd20, hd10 , or clone : tx / rx . 3 3 i f a c e 1 no spi : fd >> t x sync; hd20 or hd1 0 : tx/ rx .
AD9861 rev. 0 | page 9 of 52 pin no. name 1 description 2, 3 34 aux_spi_clk clk for auxspi. 35C44 l9Cl0 lower data bit 9 to lower data bit 0. 45 aux3 configurable as either auxadc_b or auxdac_c. 46 reset chip reset when low. 47 aux_adc_ref decoupling for auxadc on-chip reference. 48 clkin clock input. 52 refb adc bottom reference. 54, 55 vin+b, vin?b adc b differential input. 56 vref adc band gap reference. 57, 58 vin?a, vin+a adc a differential input. 60 reft adc top reference. 62 rxpwrdwn rx analog power-down control. 63 txpwrdwn tx analog power-down control. 64 spi_cs spi: serial port chip select. at powe r-up or reset, this must be high. no spi: tie low to disable spi and use mode pins. this pin must be tied low. 1 underlined pin names and descript ions apply when the device is co nfigured without a serial port interface, referred to as no s pi mode. 2 pin function depends if the serial port is used to configure the AD9861 (called sp i mode) or if mode pins are used to configur e the AD9861 (called no spi mode). the differences are indicated by the spi and no spi labels in the description column. 3 some pin descriptions depend on the inte rface configuration, full-duple x (fd), half-duplex interlea ved data (hd10), half-duple x parallel data (hd20), and a half-duplex interface similar to the ad9860 and ad9862 data interface called clon e mode (clone). clone mode re quires a serial port interfac e.
AD9861 rev. 0 | page 10 of 52 typical perf orm ance cha r acte ristics 03606-0-031 05 1 0 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?110 15 20 25 frequency (mhz) amp l itude (dbfs ) f i g u re 4. a d 98 61- 5 0 r x p a t h s i ng l e - t o n e fft of r x cha n n e l b p a t h d i giti zing 2 m h z t o ne 03606-0-033 05 1 0 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 ? 110 15 20 25 frequency (mhz) a m plitu d e ( d b f s) f i g u re 5. a d 98 61- 5 0 r x p a t h s i ng l e - t o n e fft of r x cha n n e l b p a t h d i giti zing 5 m h z t o ne 03606-0-035 05 1 0 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ? 100 ?110 15 20 25 frequency (mhz) a m plitu d e ( d b f s) f i g u re 6. a d 98 61- 5 0 r x p a t h s i ng l e - t o n e fft of r x cha n n e l b p a t h d i giti zing 2 4 mh z t o ne 03606-0-032 05 1 0 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?110 15 20 25 frequency (mhz) a m plitu d e ( d b f s) f i g u re 7. a d 98 61- 5 0 r x p a t h d u a l - t on e fft of r x chan ne l a p a t h d i giti zing 1 m h z a n d 2 m h z t o nes 03606-0-034 05 1 0 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ? 100 ?110 15 20 25 frequency (mhz) amp l itude (dbfs ) f i g u re 8. a d 98 61- 5 0 r x p a t h d u a l - t on e fft of r x chan ne l a p a t h d i giti zing 5 m h z a n d 8 m h z t o nes 03606-0-036 05 1 0 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?110 15 20 25 frequency (mhz) amp l itude (dbfs ) f i g u re 9. a d 98 61- 5 0 r x p a t h d u a l - t on e fft of r x chan ne l a p a t h d i giti zing 2 0 mh z and 25 m h z t o nes
AD9861 rev. 0 | page 11 of 52 03606-0-037 05 1 0 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?110 15 20 25 frequency (mhz) amp l itude (dbfs ) f i g u re 10. a d 9 8 6 1 - 50 r x p a t h si ng l e - t one ff t of r x ch an nel b p a t h d i giti zing 7 6 mh z t o ne 03606-0-039 05 1 0 62 59 56 53 50 15 20 25 input frequency (mhz) s nr (dbc ) normal power @ 50msps low power adc @ 25msps ultralow power adc @ 16msps f i g u re 11. a d 9 8 6 1 - 50 r x p a t h at 5 0 m s ps, 10 m h z input t o n e snr p e r f o r man c e v s . input f r equ e nc y 03606-0-041 05 1 0 80 75 55 60 65 70 50 15 20 25 input frequency (mhz) s f dr (dbc ) normal power @ 50msps low power adc @ 25msps ultralow power adc @ 16msps f i g u re 12. a d 9 8 6 1 - 50 r x p a t h at 5 0 m s ps, 10 m h z input t o n e sfdr p e r f o r man c e v s . input f r equ e nc y 03606-0-038 05 1 0 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?110 15 20 25 frequency (mhz) amp l itude (dbfs ) f i g u re 13. a d 9 8 6 1 - 50 r x p a t h d u al- t o n e fft of r x cha n n e l a p a t h d i giti zing 7 0 mh z and 72 m h z t o nes 03606-0-040 05 1 0 62 59 56 53 50 10.0 8.0 8.2 8.4 8.6 8.8 9.0 9.2 9.4 9.6 9.8 15 20 25 input frequency (mhz) s i nad (dbc ) enob ( b it s) normal power @ 50msps low power adc @ 25msps ultralow power adc @ 16msps f i g u re 14. a d 9 8 6 1 - 50 r x p a t h at 5 0 m s ps, 10 m h z input t o n e sina d p e r f or m a nce v s . input f r equen c y 03606-0-042 05 1 0 ?80 ?75 ?70 ?65 ?60 ?55 ?50 15 20 25 input frequency (mhz) thd (dbc ) normal power @ 50msps low power adc @ 25msps ultralow power adc @ 16msps f i g u re 15. a d 9 8 6 1 - 50 r x p a t h at 5 0 m s ps, 10 m h z input t o n e thd p e r f o r man c e v s . input f r equ e nc y
AD9861 rev. 0 | page 12 of 52 03606-0-043 0 ? 5 ? 10 ? 1 5 ? 20 ?25 ? 30 ?35 snr ?40 0 10 20 30 40 50 60 70 ?4 5 input amplitude (dbfs) s nr (dbc ) ideal snr f i g u re 16. a d 9 8 6 1 - 50 r x p a t h at 5 0 m s ps, 10 m h z input t o n e snr p e r f orman c e v s . input a m plitude 03606-0-045 56 57 58 59 60 61 62 ave ( ? 40 c) ave (+85 c) 2.7 3.0 3.3 3.6 adc_avdd voltage (v) s nr (dbc ) ave (+25 c) f i g u re 17. a d 9 8 6 1 - 50 r x p a t h at 5 0 m s ps, 10 m h z input t o n e snr p e r f o r man c e v s . a d c_a v dd and t e m p er ature 03606-0-047 ?75.0 ?74.5 ?74.0 ?73.5 ?73.0 ?72.5 ?72.0 ?71.5 ?71.0 ?70.5 ?70.0 ave (+85 c) input amplitude (dbfs) thd (dbc ) ave (+25 c) ave ( ? 40 c) 3.6 3.3 3.0 2.7 f i g u re 18. a d 9 8 6 1 - 50 r x p a t h si ng l e - t one thd p e r f or m a nc e v s . a d c_a v dd and t e mpe r at u r e 03606-0-044 0 ? 5 ? 10 ?15 ? 20 ?25 ? 30 ?35 20 30 40 50 60 70 80 90 ? 9 0 ?8 0 ?7 0 ?6 0 ?5 0 ?4 0 ?3 0 ?2 0 sfdr thd ?40 input amplitude (dbfs) s f dr (dbfs ) thd (dbfs ) f i g u re 19. a d 9 8 6 1 - 50 r x p a t h at 5 0 m s ps, 10 m h z input t o n e thd and sf dr p e r f ormanc e vs . input a m plitud e 03606-0-046 2.7 3.0 3.3 56 59 58 57 62 61 60 10.0 9.9 9.8 9.7 9.6 9.5 9.4 9.3 9.2 9.1 9.0 ave (+85 c) 3.6 adc_avdd voltage (v) s i nad (dbc ) enob ( b it s) ave (+25 c) ave ( ? 40 c) f i g u re 20. a d 9 8 6 1 - 50 r x p a t h at 5 0 m s ps, 10 m h z input t o n e sinad p e r f or mance vs. adc_a v dd and t e mp e r atu r e 03606-0-048 3.6 3.3 3.0 78 70 71 72 73 74 75 76 77 ave (+85 c) 2.7 input amplitude (dbfs) s f dr (dbc ) ave (+25 c) ave ( ? 40 c) f i g u re 21. a d 9 8 6 1 - 50 r x p a t h si ng l e - t one sfdr p e r f or m a nc e v s . a d c_a v dd and t e mpe r at u r e
AD9861 rev. 0 | page 13 of 52 03606-0-049 0 5 10 15 20 25 30 35 ?110 ? 100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 40 frequency (mhz) amp l itude (dbfs ) f i g u re 22. a d 9 8 6 1 - 80 r x p a t h si ng l e - t one ff t of r x ch an nel b p a t h d i giti zing 2 m h z t o ne 03606-0-051 0 5 10 15 20 25 30 35 ?110 ? 100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 40 frequency (mhz) amp l itude (dbfs ) f i g u re 23. a d 9 8 6 1 - 80 r x p a t h si ng l e - t one ff t of r x ch an nel b p a t h d i giti zing 5 m h z t o ne 03606-0-053 0 5 10 15 20 25 30 35 ?110 ? 100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 40 frequency (mhz) amp l itude (dbfs ) f i g u re 24. a d 9 8 6 1 - 80 r x p a t h si ng l e - t one ff t of r x ch an nel b p a t h d i giti zing 2 4 mh z t o ne 03606-0-050 0 5 10 15 20 ?110 ? 100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 25 frequency (mhz) amp l itude (dbfs ) f i g u re 25. a d 9 8 6 1 - 80 r x p a t h d u al- t o n e fft of r x cha n n e l a p a t h d i giti zing 1 m h z a n d 2 m h z t o nes 03606-0-052 0 5 10 15 20 ?110 ? 100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 25 frequency (mhz) amp l itude (dbfs ) f i g u re 26. a d 9 8 6 1 - 80 r x p a t h d u al- t o n e fft of r x cha n n e l a p a t h d i giti zing 5 m h z a n d 8 m h z t o nes 03606-0-054 0 5 10 15 20 ?110 ? 100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 25 frequency (mhz) amp l itude (dbfs ) f i g u re 27. a d 9 8 6 1 - 80 r x p a t h d u al- t o n e fft of r x cha n n e l a p a t h d i giti zing 2 0 mh z and 25 m h z t o nes
AD9861 rev. 0 | page 14 of 52 03606-0-055 0 5 10 15 20 50 53 56 59 62 30 25 input frequency (mhz) s nr (dbc ) normal power @ 80msps low power adc @ 40msps ultralow power adc @ 16msps f i g u re 28. a d 9 8 6 1 - 80 r x p a t h at 8 0 m s ps, 10 m h z input t o n e snr p e r f orm a nc e v s . input f r equenc y a n d p o w e r s e tti ng 03606-0-057 0 5 10 15 20 60 80 75 70 65 85 25 input frequency (mhz) s f dr (dbc ) normal power @ 80msps low power adc @ 40msps ultralow power adc @ 16msps f i g u re 29. a d 9 8 6 1 - 80 r x p a t h at 8 0 m s ps, 10 m h z input t o n e sfdr p e r f or man c e vs. input f r equ e nc y and p o wer s e tting 03606-0-059 0 ? 5 ? 10 ? 1 5 ? 20 ?25 ? 30 ?35 snr ?40 0 10 20 30 40 50 60 70 ?4 5 input amplitude (dbfs) s nr (dbc ) ideal snr f i g u re 30. a d 9 8 6 1 - 80 r x p a t h at 8 0 m s ps, 10 m h z input t o n e snr p e r f orman c e v s . input a m plitude 03606-0-056 0 5 10 15 20 50 53 56 59 62 10.0 9.8 9.6 9.4 9.2 9.0 8.8 8.6 8.4 8.2 8.0 30 25 input frequency (mhz) s i nad (dbc ) enob ( b it s) normal power @ 80msps low power adc @ 40msps ultralow power adc @ 16msps f i g u re 31. a d 9 8 6 1 - 80 r x p a t h at 8 0 m s ps, 10 m h z input t o n e sina d p e r f or m a nce v s . input f r equen c y and p o w e r s e tti ng 03606-0-058 0 5 10 15 20 ?8 0 ?7 5 ?5 5 ?6 0 ?6 5 ?7 0 ?5 0 25 input frequency (mhz) thd (dbc ) ultralow power adc @ 16msps normal power @ 80msps low power adc @ 40msps f i g u re 32. a d 9 8 6 1 - 80 r x p a t h at 8 0 m s ps, 10 m h z input t o n e thd p e r f or man c e vs. input f r equ e nc y and p o wer s e tting 03606-0-060 0 ? 5 ? 10 ?15 ? 20 ? 2 5 ? 30 ?35 ?2 0 ?3 0 ?4 0 ?5 0 ?6 0 ?7 0 ?8 0 8 0 70 60 50 40 30 20 thd ?40 input amplitude (dbfs) thd (dbfs ) s f dr (dbfs ) sfdr f i g u re 33. a d 9 8 6 1 - 80 r x p a t h at 8 0 m s ps, 10 m h z input t o n e thd p e r f o r man c e v s . input a m plitud e
AD9861 rev. 0 | page 15 of 52 03606-0-065 ave ( ? 40 c) ave (+25 c) ave (+85 c) 56 57 58 59 60 61 62 2.7 3.0 3.3 3.6 adc_avdd voltage (v) s nr (dbc ) f i g u re 34. a d 9 8 6 1 - 80 r x p a t h at 8 0 m s ps, 10 m h z input t o n e snr p e r f o r man c e v s . a v dd and t e mper atu r e 03606-0-061 60 61 62 63 64 65 66 67 68 69 70 adc_avdd voltage (v) thd (dbc ) ave (+85 c) ave (+25 c) ave ( ? 40 c) 2.7 3.0 3.3 3.6 f i g u re 35. a d 9 8 6 1 - 80 r x p a t h at 8 0 m s ps, 10 m h z input t o n e thd p e r f o r man c e v s . a v dd and t e m p er atu r e 03606-0-063 04 30 20 10 0 20 40 60 80 100 120 ulp lp norm 50 f clk (mhz) adc av dd curre nt (ma) 0 f i g u re 36. a d 9 8 6 1 - 50 a d c _ a v dd cu r r ent v s . s a mp li ng r a te f o r d i ffer e nt adc p o wer l e vels 03606-0-066 2.7 3.0 3.3 ave ( ? 40 c) ave (+25 c) ave (+85 c) 56 59 62 61 60 58 57 9.0 10.0 9.9 9.8 9.7 9.6 9.5 9.4 9.2 9.1 9.3 3.6 adc_avdd voltage (v) s i nad (dbc ) enob ( b it s) f i g u re 37. a d 9 8 6 1 - 80 r x p a t h at 8 0 m s ps, 10 m h z input t o n e sinad p e r f or mance vs. a v dd and t e mp e r atu r e 03606-0-062 75 74 73 72 71 70 69 68 67 66 65 adc_avdd voltage (v) s f dr (dbc ) ave (+85 c) ave (+25 c) ave ( ? 40 c) 2.7 3.0 3.3 3.6 f i g u re 38. a d 9 8 6 1 - 80 r x p a t h at 8 0 m s ps, 10 m h z input t o n e sfdr p e r f o r man c e v s . a v dd and t e m p er atu r e 03606-0-064 0 4 05 0 6 07 0 30 20 10 0 20 40 60 80 100 180 120 140 160 ulp lp 80 f clk (mhz) adc av dd curre nt (ma) norm f i g u re 39. a d 9 8 6 1 - 80 a d c _ a v dd cu r r ent v s . a d c s a mpl i ng r a te f o r d i ffer e nt adc p o wer l e vels
AD9861 rev. 0 | page 16 of 52 03606-0-068 0 1 01 52 0 5 ? 110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 25 frequency (mhz) a m plitu d e ( d b c ) f i gure 40. ad9 8 6 1 t x p a th 1 mh z s i ng le - t on e o u tput fft of t x p a th wit h 20 ma f u l l -s c a l e o u t p ut in to 3 3 ? d i f f e r e nt ia l l o ad 03606-0-070 01 0 1 5 2 0 5 ?110 ?100 ?9 0 ?8 0 ?7 0 ?6 0 ?5 0 ?4 0 ?3 0 ?2 0 ?1 0 0 25 frequency (mhz) amp l itude (dbc ) f i gure 41. ad9 8 6 1 t x p a th 1 mh z s i ng le - t on e o u tput fft of t x p a th wit h 20 ma f u l l -s c a l e o u t p ut in to 6 0 ? d i f f e r e nt ia l l o ad 03606-0-072 01 0 1 5 2 0 5 ?110 ?100 ?9 0 ?8 0 ?7 0 ?6 0 ?5 0 ?4 0 ?3 0 ?2 0 ?1 0 0 25 frequency (mhz) amp l itude (dbc ) f i gure 42. ad9 8 6 1 t x p a th 1 mh z s i ng le - t on e o u tput fft of t x p a th wit h 2 ma f u ll- s c a l e o u t p ut int o 6 0 0 ? d i f f e r e nt ia l l o ad 03606-0-069 01 0 1 5 2 0 5 ?110 ?100 ?9 0 ?8 0 ?7 0 ?6 0 ?5 0 ?4 0 ?3 0 ?2 0 ?1 0 0 25 frequency (mhz) a m plitu d e ( d b c ) f i gure 43. ad9 8 6 1 t x p a th 5 mh z s i ng le - t on e o u tput fft of t x p a th wit h 20 ma f u l l -s c a l e o u t p ut in to 3 3 ? d i f f e r e nt ia l l o ad 03606-0-071 01 0 1 5 2 0 5 ?110 ?100 ?9 0 ?8 0 ?7 0 ?6 0 ?5 0 ?4 0 ?3 0 ?2 0 ?1 0 0 25 frequency (mhz) amp l itude (dbc ) f i gure 44. ad9 8 6 1 t x p a th 5 mh z s i ng le - t on e o u tput fft of t x p a th wit h 20 ma f u l l -s c a l e o u t p ut in to 6 0 ? d i f f e r e nt ia l l o ad 03606-0-073 01 0 1 5 2 0 5 ?110 ?100 ?9 0 ?8 0 ?7 0 ?6 0 ?5 0 ?4 0 ?3 0 ?2 0 ?1 0 0 25 frequency (mhz) amp l itude (dbc ) f i gure 45. ad9 8 6 1 t x p a th 5 mh z s i ng le - t on e o u tput fft of t x p a th wit h 2 ma f u ll- s c a l e o u t p ut int o 6 0 0 ? d i f f e r e nt ia l l o ad
AD9861 rev. 0 | page 17 of 52 03606-0-074 01 0 1 5 2 0 5 ?100 ?9 0 ?8 0 ?7 0 ?6 0 ?5 0 25 output frequency (mhz) thd (dbc) f i gure 4 6 . ad98 61 t x p a th th d vs . o u tput f r equenc y o f t x p a th wi th 20 ma f u l l -s c a le o u t p ut into 6 0 ? d i f f e r e nt ia l l o ad 03606-0-076 01 0 1 5 2 0 5 56 57 58 59 60 61 62 25 output frequency (mhz) s i nad (dbc ) f i gur e 4 7 . ad98 61 t x p a th sinad vs . o u tput f r equenc y o f t x p a th, wi th 20 ma f u l l -s c a le o u t p ut into 6 0 ? d i f f e r e nt ia l l o ad 03606-0-078 01 0 1 5 2 0 5 ?9 5 ?7 0 ?7 5 ?8 0 ?8 5 ?9 0 25 output frequency (mhz) imd (dbc ) f i gur e 4 8 . ad98 61 t x p a th d u al - t one (0 .5 mhz spac ing) imd vs . o u tput f r equenc y o f t x p a th, wi th 20 ma f u l l -s c a le o u t p ut into 6 0 ? d i f f e r e nt ia l l o ad 03606-0-075 01 0 1 5 2 0 5 ?100 ?5 0 ?6 0 ?7 0 ?8 0 ?9 0 25 output frequency (mhz) thd (dbc) f i gure 4 9 . ad98 61 t x p a th th d vs . o u tput f r equenc y o f t x p a th wit h 2 ma f u ll- s c al e o u t p ut int o 60 0 ? d i f f e r e nt ia l l o ad 03606-0-077 01 0 1 5 2 0 5 56 57 58 59 60 61 62 25 output frequency (mhz) s i nad (dbc ) f i gur e 5 0 . ad98 61 t x p a th sinad vs . o u tput f r equenc y o f t x p a th, wi th 2 m a f u l l - sc a l e output i n t o 60 0 ? di ff e r enti al l o a d 03606-0-079 01 0 1 5 2 0 5 ?9 5 ?7 0 ?7 5 ?8 0 ?8 5 ?9 0 25 output frequency (mhz) imd (dbc ) f i gur e 5 1 . ad98 61 t x p a th d u al - t one (0 .5 mhz spac ing) imd vs . o u tput f r equenc y o f t x p a th, wi th 2 m a f u l l - sc a l e output i n t o 60 0 ? di ff e r enti al l o a d
AD9861 rev. 0 | page 18 of 52 f i gur e 52 t o f i gur e 57 us e th e s a me in p u t da ta t o th e tx p a th, a 64-ca r r i er o f d m sig n al o v er a 20 mh z ban d wid t h, cen t er e d a t 20 mh z . the ce n t er tw o ca r r i ers a r e r e m o v e d f r o m t h e s i g n al t o obs e r v e t h e i n -b an d i n ter m o d u l a t ion dis t o r t i o n (imd) f r o m t h e d a c o u t p ut . 03606-0-080 7.5 17.5 22.5 27.5 12.5 ?130 ?120 ?110 ?100 ?9 0 ?8 0 ?7 0 ?6 0 ?5 0 ?4 0 ?3 0 32.5 frequency (mhz) amp l itude (dbc ) f i gure 52. a d 9 8 6 1 t x p a th fft , 6 4 - c ar rie r (cen ter t w o ca rri ers r e m o ved) ofdm sign al o v e r 20 m h z bandwidth , centered at 2 0 m h z, with 20 ma f u l l -s c a le o u t p ut into 6 0 ? d i f f e r e nt ia l l o ad 03606-0-082 7.5 8.0 8.5 9.0 9.5 10.0 10.5 11.0 11.5 12.0 ?130 ?120 ?110 ?100 ?9 0 ?8 0 ?7 0 ?6 0 ?5 0 ?4 0 ?3 0 12.5 frequency (mhz) amp l itude (dbc ) f i gure 53. AD9861 t x p a th fft , l o wer - band im d pr oduc ts of ofdm sign al in f i g u r e 52 03606-0-084 0 1 02 03 04 05 0 6 07 0 ?130 ?120 ?110 ?100 ?9 0 ?8 0 ?7 0 ?6 0 ?5 0 ?4 0 ?3 0 80 frequency (mhz) amp l itude (dbc ) f i gur e 5 4 . ad98 61 t x p a th fft of ofd m sig n al in f i g u r e 52, with 1 i n te rp olat ion 03606-0-081 18.75 19.75 20.25 20.75 19.25 ?130 ?120 ?110 ?100 ?9 0 ?8 0 ?7 0 ?6 0 ?5 0 ?4 0 ?3 0 21.25 frequency (mhz) amp l itude (dbc ) f i g u re 55. a d 9 8 6 1 t x p a t h fft , in-b an d im d pr oduc t s of ofdm sign al in f i g u r e 52 03606-0-083 27.5 28.0 28.5 29.0 29.5 30.0 30.5 31.0 31.5 32.0 ?130 ?120 ?110 ?100 ?9 0 ?8 0 ?7 0 ?6 0 ?5 0 ?4 0 ?3 0 32.5 frequency (mhz) amp l itude (dbc ) f i g u re 56. a d 9 8 6 1 t x p a t h fft , u p pe r - band im d pr oduc t s of ofdm sign al in f i g u r e 52 03606-0-085 0 1 02 03 04 05 0 6 07 0 ?130 ?120 ?110 ?100 ?9 0 ?8 0 ?7 0 ?6 0 ?5 0 ?4 0 ?3 0 80 frequency (mhz) amp l itude (dbc ) f i gur e 5 7 . ad98 61 t x p a th fft of ofd m sig n al in f i g u r e 52, with 4 i n te rp olat ion
AD9861 rev. 0 | page 19 of 52 f i gur e 58 t o f i gur e 63 us e th e s a me in p u t da ta t o th e tx p a th, a 256-ca r r i er o f d m sig n al o v er a 1.75 mh z ban d wid t h, cen t er ed a t 7 mh z. the ce n t er fo ur ca r r i ers a r e r e m o v e d f r o m t h e s i g n al t o obs e r v e t h e in-b an d in ter m o d u l a t ion dis t o r t i o n (imd) f r o m t h e d a c o u t p u t. 03606-0-086 6.0 6.2 6.4 6.6 6.8 7.0 7.2 7.4 7.6 7.8 ?130 ?140 ?120 ?110 ?100 ?9 0 ?8 0 ?7 0 ?6 0 ?5 0 ?4 0 8.0 frequency (mhz) amp l itude (dbc ) f i gur e 5 8 . ad98 61 t x p a th fft , 256 - c a r ri er ( c e n t e r f o ur c a r r i e r s re mo v e d) ofdm sign al o v e r 1.75 m h z b a nd wid t h, c e ntered at 7 m h z, with 20 ma f u l l -s c a le o u t p ut into 6 0 ? d i f f e r e nt ia l l o ad 03606-0-088 6.06 6.08 6.10 6.12 6.14 6.16 ?130 ?140 ?120 ?110 ?100 ?9 0 ?8 0 ?7 0 ?6 0 ?5 0 ?4 0 6.18 frequency (mhz) a m plitu d e ( d b c ) f i gure 59. AD9861 t x p a th fft , l o wer - band im d pr oduc ts of ofdm sign al in f i g u r e 58 03606-0-090 0 5 10 15 20 25 ?130 ?120 ?110 ?100 ?9 0 ?8 0 ?7 0 ?6 0 ?5 0 ?4 0 ?3 0 frequency (mhz) amp l i t ude (dbc ) f i gur e 6 0 . ad98 61 t x p a th fft of ofd m sig n al in f i g u r e 52, with 1 i n te rp olat ion 03606-0-087 6.97 6.98 6.99 7.00 7.01 7.02 ?130 ?140 ?120 ?110 ?100 ?9 0 ?8 0 ?7 0 ?6 0 ?5 0 ?4 0 7.03 frequency (mhz) amp l itude (dbc ) f i g u re 61. a d 9 8 6 1 t x p a t h fft , in-b an d im d pr oduc t s of ofdm sign al in f i g u r e 58 03606-0-089 7.81 7.83 7.85 7.87 7.89 7.91 ?130 ?140 ?120 ?110 ?100 ?9 0 ?8 0 ?7 0 ?6 0 ?5 0 ?4 0 7.93 frequency (mhz) a m plitu d e ( d b c ) f i g u re 62. a d 9 8 6 1 t x p a t h fft , u p pe r - band im d pr oduc t s of ofdm sign al in f i g u r e 52 03606-0-091 0 5 10 15 20 25 ?130 ?120 ?110 ?100 ?9 0 ?8 0 ?7 0 ?6 0 ?5 0 ?4 0 ?3 0 frequency (mhz) amp l i t ude (dbc ) f i gur e 6 3 . ad98 61 t x p a th fft of ofd m sig n al in f i g u r e 52, with 4 i n te rp olat ion
AD9861 rev. 0 | page 20 of 52 f i gur e 64 t o f i gur e 69 us e th e s a me in p u t da ta t o th e tx p a th, a 256-ca r r ier o f d m sig n al o v er a 23 mh z b a nd wid t h, cen t er e d a t 2 3 m h z. the ce n t er fo ur ca r r i ers a r e r e m o v e d f r o m t h e s i g n al t o obs e r v e t h e i n -b an d i n ter m o d u l a t ion dis t o r t i o n (imd) f r o m t h e d a c o u t p u t. 03606-0-092 9 1 41 9 2 42 9 3 4 ?130 ?140 ?120 ?110 ?100 ?9 0 ?8 0 ?7 0 ?6 0 ?5 0 ?4 0 frequency (mhz) amp l itude (dbc ) f i gur e 6 4 . ad98 61 t x p a th fft , 256 - c a r ri er ( c e n t e r f o ur c a r r i e r s re mo v e d) ofdm sign al o v e r 23 m h z bandwidt h , centered at 7 m h z, w i th 20 ma f u l l -s c a le o u t p ut into 6 0 ? d i f f e r e nt ia l l o ad 03606-0-094 10.5 10.7 10.9 11.1 11.3 11.5 11.7 11.9 12.1 12.3 12.5 ?130 ?140 ?120 ?110 ?100 ?9 0 ?8 0 ?7 0 ?6 0 ?5 0 ?4 0 frequency (mhz) a m plitu d e ( d b c ) f i gure 65. AD9861 t x p a th fft , l o wer - band im d pr oduc ts of ofdm sign al in f i g u r e 64 03606-0-096 0 1 0 2 03 04 0 5 06 07 0 8 09 0 ?130 ?120 ?110 ?100 ?9 0 ?8 0 ?7 0 ?6 0 ?5 0 ?4 0 ?3 0 frequency (mhz) amp l itude (dbc ) f i gur e 6 6 . ad98 61 t x p a th fft of ofd m sig n al in f i g u r e 52 with 1 i n te rp olat ion 03606-0-093 22.6 22.7 22.8 22.9 23.0 23.1 23.2 23.3 23.4 ?130 ?140 ?120 ?110 ?100 ?9 0 ?8 0 ?7 0 ?6 0 ?5 0 ?4 0 frequency (mhz) amp l itude (dbc ) f i g u re 67. a d 9 8 6 1 t x p a t h fft , in-b an d im d pr oduc t s of ofdm sign al in f i g u r e 64 03606-0-095 33.5 33.7 33.9 34.1 34.3 34.5 34.7 34.9 35.1 35.3 35.5 ?130 ?140 ?120 ?110 ?100 ?9 0 ?8 0 ?7 0 ?6 0 ?5 0 ?4 0 frequency (mhz) amp l i t ude (dbc ) f i g u re 68. a d 9 8 6 1 t x p a t h fft , u p pe r - band im d pr oduc t s of ofdm sign al in f i g u r e 64 03606-0-097 0 1 0 2 03 04 0 5 06 07 0 8 09 0 ?130 ?120 ?110 ?100 ?9 0 ?8 0 ?7 0 ?6 0 ?5 0 ?4 0 ?3 0 frequency (mhz) amp l itude (dbc ) f i gur e 6 9 . ad98 61 t x p a th fft of ofd m sig n al in f i g u r e 52 with 4 i n te rp olat ion
AD9861 rev. 0 | page 21 of 52 terminology i nput b a n d w i d t h the a n alog in pu t f r e q uen c y a t w h ich t h e s p e c t r al p o w e r o f t h e f u ndam e n t a l f r e q uen c y (as de t e r m in e d b y t h e fft a n a l y s is) is re d u c e d by 3 d b . ap e r t u r e d e l a y the dela y b e tw e e n t h e 50% p o i n t o f t h e r i sin g e d g e o f t h e clki n sig n a l and t h e in st an t a t w h ich t h e a n a l og in p u t is ac t u a l ly s a m p le d . ap e r t u r e un c e r t a i n t y ( j i t t e r ) the s a m p le-t o-s a m p le va r i a t ion in a p er t u r e dela y . cr o s s t alk c o u p lin g o n t o o n e c h a n n e l bein g dr i v en b y a C0.5 db fs sig n al w h en t h e ad jac e n t i n t e r f er in g cha n n e l is dr i v e n b y a f u l l -s cale sig n al . d i f f erenti a l a n a l o g i n put v o lt a g e r a ng e the p e a k -t o - p e ak dif f er en t i al vol t a g e t h a t m u st b e a p plie d t o t h e con v er t e r t o g e n e r a t e a f u l l - s cale r e s p o n s e . p e ak dif f er en t i a l v o l t a g e is com p u t e d b y obs e r v i n g t h e v o l t a g e on a sin g le p i n a nd sub t r a c t i n g t h e vol t a g e f r o m t h e o t h e r p i n, w h ich is 180 o u t o f p h as e . p e ak-t o-p e a k dif f er en tial is com p u t ed b y r o ta t i n g th e in p u t p h as e 180 a nd ta kin g th e p e ak m e as u r em en t a g ain. then t h e dif f er en ce is com p ut e d b e twe e n b o t h p e ak me a s u r e m e n t s . d i f f erenti a l n o n l i n e a r i ty t h e devia t i o n o f a n y cod e w i d t h f r o m a n id eal 1 l s b s t e p . e f f e c t iv e n u mb er of b i ts (eno b) the ef fe c t i v e n u m b er o f b i ts is c a lc u l a t e d f r o m t h e m e as ur e d sn r b a s e d on t h e f o l l ow i n g e q u a t i o n : 02 . 6 76 . 1 db snr enob measured ? = pu ls e w i d t h/d u ty cy cl e pulse w i d t h h i g h i s th e m i ni m u m a m o u n t o f tim e tha t a si gn al s h o u ld b e lef t in th e log i c hig h sta t e t o ac hie v e r a t e d p e r f o r m- a n c e ; p u ls e wid t h lo w is th e minim u m tim e a sig n al s h o u l d b e lef t in t h e lo w s t a t e , log i c lo w . f u ll - s c a le i n p u t p o w e r e x p r es s e d in dbm, f u l l -s cale in p u t p o w e r is co m p u t e d usin g the f o l l ow i n g e q u a t i on : ? ? ? ? ? ? ? ? = ? 001 . 0 log 10 2 input rms fullscale fullscale z v power gain error g a i n e r r o r i s th e d i f f e r e n ce betw ee n t h e m e a s ur ed a n d id eal f u l l -s cale i n p u t v o l t a g e ra n g e o f t h e ad c. ha r m o n i c d i s t or t i on , s e c o n d the ra t i o o f t h e r m s sig n al a m pl i t ude t o t h e r m s val u e o f t h e s e con d ha r m o n ic co m p on en t, rep o r t ed in db c. ha r m o n i c d i s t or t i on , t h i r d the ra t i o o f t h e r m s sig n al a m pl i t ude t o t h e r m s val u e o f t h e th i r d h a rm o n i c co m p o n en t , r e p o r t ed i n d b c. in t e g r a l no n l i n e a r i t y the de v i a t ion of t h e t r a n sfer f u n c t i on f r o m a refer e n c e li n e m e as ur ed in f r ac tio n s o f a n ls b usin g a b est stra ig h t line det e r m i n e d b y a le as t s q ua r e c u r v e f i t. minim u m c o n v ersi on r a t e the e n co de ra te a t w h ich t h e snr o f t h e lo w e s t a n alog sig n al f r e q u e nc y d rop s by no more t h an 3 d b b e l o w t h e g u ar an te e d limi t. max i mu m c o n v er si on r a te the e n co d e ra te a t w h ich p a ramet r ic t e st in g is p e r f o r m e d . ou t p u t p r o p aga t io n d e la y the dela y b e tw e e n a dif f er en t i al cr os sin g o f clk+ an d c l k ? a n d t h e tim e w h en all o u t p u t da ta b i t s a r e w i t h i n v a lid logi c lev e ls. po w e r s u p p l y r e j e c t i o n r a t i o the ra t i o o f a cha n g e i n i n p u t o f fs et v o l t a g e t o a cha n g e in po w e r s u p p l y v o l t a g e . s i g n a l -t o-n o is e an d dis t o r t i o n (s in ad) the ra t i o o f t h e r m s sig n al a m pl i t ude (s et 1 db b e lo w f u l l -s cale ) t o th e rm s v a l u e o f th e s u m o f al l o t h e r s p ectral co m p o n en t s , in cl u d in g h a r m o n ics, b u t excl u d in g dc . s i g n a l -t o-n o is e r a ti o (w itho ut h a rmo n i c s) the ra t i o o f t h e r m s sig n al a m pl i t ude (s et a t 1 db b e lo w f u l l s c ale) t o t h e r m s val u e o f t h e s u m o f al l o t h e r sp e c t r al co m p on e n ts, excl udin g t h e f i rs t f i v e ha r m o n ics a nd dc. s p uri o us-f r e e d y na mi c r a n g e (s fd r) the ra t i o o f t h e r m s sig n al a m pl i t ude t o t h e r m s val u e o f t h e p e ak sp ur io us s p ec tral co m p onen t. the p e a k s p ur io us co m p o n en t ma y o r m a y n o t be a h a r m o n ic. i t a l so m a y be r e p o r t e d in db c ( i .e., deg r ades a s sig n a l le vel is l o w e r e d) o r db fs (i .e., al wa ys r e la t e d back to co n v er t e r f u l l s c ale). s f d r do es n o t i n cl ude ha r m o n ic dis t o r t i o n co m p on e n ts. wo r s t o t h e r s p u r the ra t i o o f t h e r m s sig n al a m pl i t ude t o t h e r m s val u e o f t h e w o rst sp ur io us co m p on e n t ( e xcl u din g t h e s e cond an d t h ir d h a r m on i c s ) re p o r t e d i n d b c .
AD9861 rev. 0 | page 22 of 52 theory of operation system block the AD9861 is targeted to cover the mixed-sig n al front end nee d s of mult ip le wirel e ss communication syst ems. it fe atures a receive p a t h th a t consist s of dua l 10-bit rec e iv e adcs, an d a trans m i t pat h t h at co nsis ts of dual 10-b i t tr ans m it dacs (txdac). the AD9861 integr a tes additio n al fu nctio n al ity typically requir ed in mos t syste m s, such as po wer scal abil ity, ad dit i on al auxil i ary convert e rs, tx gai n con t rol, an d clock multiplication c i rcuitry. the AD9861 minimizes bo th size and po we r consumption to add r ess th e n e ed s of a range of applications from the low power portable market to the hig h pe rform an ce base statio n market. the part is prov ide d i n a 64 -lead lead frame chi p scale pac k ag e (lfcsp) th at has a footprint of on ly 9 m m 9 m m . power consumpt ion c a n be opt i miz e d to suit t h e part i c ular applic atio n beyon d just a speed grad e option by in corporatin g power-d o wn con t rols, low power adc m o des, txda c powe r scaling , a nd a half- d uplex mode, w h ic h au tomat i cally dis a bl es the u n us ed dig i tal p a t h . the AD9861 us es two 10-bit bu ses to transfer rx path data and tx pat h data. these t w o buse s support 20-bit parallel d a ta transfers or 10- bit int e rleaved dat a transfers. the bus i s con f igur able through eith er extern al m o d e pins or th rough int e rnal regist ers setti ngs. th e registers allow many more options for configuring the enti re dev i ce. the fol l o w ing se ct io ns discu ss t h e var i o u s bloc ks of t h e ad986 1: rx block, tx bl ock, the auxil i ar y converters, t h e dig i t a l block, program m able registers and the clock d i stribution block. rx path bl ock rx path g e neral descri ption the AD9861 rx p a th co n s ists o f tw o 10-b i t, 50 ms ps (f o r th e AD9861-50) o r 80 ms ps (f o r th e AD9861 -80) analog-t o-dig i tal co n v er t e rs (ad c s). the d u al a d c p a t h s s h a r e t h e s a me cl o c k i ng a n d re f e re nc e c i rc u i t r y to prov i d e opt i m a l m a tch i ng cha r ac t e r i s t ics. e a ch o f t h e ad cs co n s is ts o f a 9-s t a g e dif f er en - tial p i p e lin e d s w i t ch e d c a p a ci to r a r c h i t ec t u r e wi t h o u t p u t er r o r co rr ecti o n logi c. the p i p e li ne d ar chi t e c t u r e p e r m i t s t h e f i rs t s t ag e t o o p era te o n a ne w i n p u t s a m p le , w h i l e t h e r e ma ini n g s t a g es o p era te o n p r ecedi n g sa m p le s . sa m p li n g occur s o n th e fallin g ed g e o f t h e in p u t clo c k. e a ch s t a g e o f t h e p i p e li n e , excl uding t h e l a st, c o ns i s t s of a l o w re s o lut i on f l a s h a d c a n d a r e s i d u a l m u lt ipl i e r t o dr i v e t h e n e x t s t a g e o f t h e pi p e li n e . the r e sid u al m u l t i p lier us es t h e f l ash a d c o u t p u t t o c o n t r o l a s w i t ch e d c a p a ci t o r dig i t a l-t o - a nalog co n v er t e r (d a c ) o f t h e s a m e res o l u t i o n . th e d a c o u t p u t is su b t rac t e d f r o m t h e st a g e s in p u t sig n al , a nd t h e r e sid u a l is am pl if ie d (m u l t i plie d) t o dr i v e t h e next p i p e li n e s t a g e . th e r e sid u al m u l t i p lier s t a g e is als o cal l e d a m u l t i p ly in g d a c (md a c). on e b i t o f r e d u ndan c y is us e d i n e a ch one o f t h e st a g es t o faci li t a t e dig i t a l cor r e c t i o n o f f l as h er r o rs. th e las t s t a g e si m p ly con s is ts o f a f l ash ad c. the dif f er en t i al in p u t s t a g e is dc s e lf-b i a s e d an d al lo ws dif f er en t i al o r si n g le-e n d e d i n pu ts. th e o u t p u t - s t a g i n g b l o c k alig n s t h e da t a , ca r r i es o u t t h e e r r o r co r r e c t i o n , a nd p a s s es t h e da ta t o th e o u t p u t b u f f e r s . the l a t e n c y o f t h e rx p a t h is ab o u t 5 clo c k c y cles. r x path an alo g inp u t e qui v a lent c i rc uit the rx p a t h a n alog in p u ts o f t h e AD9861 in cor p o r a t e a n o v e l s t r u c t ur e t h a t merg es t h e f u n c t i o n o f t h e i n p u t s a m p le- a n d - h o ld am plif iers (s h a s) and t h e f i rst p i p e li n e r e sid u e am plif iers in t o a sin g le , com p ac t s w i t ch e d ca p a ci t o r cir c ui t. this s t r u c t ur e achie v es con s idera b le n o i s e and p o w e r s a vin g s o v er a c o n v e n - ti o n al i m p l e m e n ta ti o n th a t us e s s e pa ra t e a m p l i f i e r s b y e l i m i n a t i n g o n e am plif ier i n t h e pi p e li n e . f i gur e 70 il l u s t ra t e s t h e e q ui val e n t a n alog in p u ts o f th e ad986 1 (a swi t ch e d c a p a ci t o r in p u t). b r in g i n g clk t o l o g i c hig h o p en s swi t ch s3 an d c l os es swi t ch es s1 a nd s2; this is t h e s a m p le m o de o f t h e in p u t cir c ui t. th e i n p u t s o ur ce co nne c t e d t o vin+ and vin? m u st c h arg e ca p a ci t o r c h d u ri n g th i s tim e . b r i n gi n g cl k t o a logi c lo w o p e n s s2, a n d t h en sw i t c h s1 o p en s f o llo w ed b y closin g s3. this p u ts t h e i n p u t c i r c ui t in t o h o ld m o de . 03606-0-002 vin+ r in v cm c in c h s1 s3 s2 c h c in r in vin? + ? f i g u re 70. d i f f e r e nt ia l input a r ch itec t u r e the s t r u c t ur e of t h e in p u t sh a places cer t a i n r e q u ir e m en ts o n t h e i n p u t dr i v e s o ur ce . the dif f er en t i a l in p u t r e sis t o r s a r e typ i cal l y 2 k? e a ch. th e com b i n a t ion o f t h e pi n c a p a ci t a n c e , c in , a n d th e h o ld ca pa c i ta n c e , c h , is typ i cal l y less tha n 5 pf . th e in p u t s o ur ce m u s t be ab le t o c h a r g e o r dis c ha r g e this ca p a c i - t a nce t o 10- b i t acc u rac y in o n e - half o f a clo c k c y cle . w h en t h e s h a g o es i n t o s a m p le m o de , t h e in p u t s o ur ce m u s t cha r g e o r d i sc h a r g e ca pa ci t o r c h f rom t h e vo lt age a l re a d y store d o n it to t h e ne w v o l t a g e . i n t h e w o rs t cas e , a f u l l -s c a le vol t a g e st ep o n t h e i n p u t s o ur ce m u s t p r o v ide t h e cha r g i ng c u r r en t t h r o u g h t h e r on o f swi t c h s 1 (typ ical l y 100 ?) t o a s e t t le d vol t a g e wi t h in o n e - half o f t h e ad c s a m p le p e r i o d . this si t u a t io n co r r es p o nds to dr i v i n g a lo w in p u t im p e dance. on t h e o t h e r ha nd , w h e n t h e s o ur ce v o l t a g e e q uals t h e val u e p r e v io us ly s t o r e d o n c h , t h e h o ld c a p a c i t o r r e q u ir es n o i n p u t c u r r en t a nd t h e e q ui vale n t in p u t im p e dan c e is ext r em e l y hi g h .
AD9861 rev. 0 | page 23 of 52 rx path a ppli c ation s e ction a d d i n g se ri e s r e s i s t a n ce be tw een th e o u t p u t o f th e s i gn al so ur ce a nd t h e vi n p i n s r e d u ces t h e dr i v e r e q u ir em e n ts place d o n t h e sig n a l s o ur ce . f i gur e 71 sh o w s t h is co nf igura t ion. 03606-0-003 r series r series vin+ c shunt AD9861 vin? f i gure 71. t y pic a l i n put the b a ndwid t h o f t h e p a r t ic u l ar a p plic a t io n l i mi ts t h e si z e o f t h is r e sist o r . f o r a p plic a t io ns w i t h sig n a l b a nd w i d t h s less t h an 10 mh z, t h e us er ma y in s e r t s e r i es in p u t r e sis t o r s a n d a sh un t ca p a c i t o r t o p r o d uce a lo w-p a s s f i l t er fo r t h e in p u t sig n al. a d di t i o n al ly , addin g a s h u n t ca p a ci t a n c e b e tw e e n t h e vi n p i n s ca n lo w e r t h e ac lo ad im p e dan c e . the val u e o f t h is ca p a c i t a n c e dep e n d s on t h e s o ur ce r e sis t a n c e a nd t h e r e q u ire d sig n al ba n d w id th . the rx i n p u t pi n s a r e s e lf- b ias e d t o p r o v ide t h i s mids u p ply , co mm o n -mo d e b i as v o l t a g e , s o i t is r e co mm ended t o ac co u p l e th e s i gn al t o th e i n p u ts us i n g d c b l oc ki n g ca pa ci t o r s . i n s y s t em s tha t m u s t us e dc co u p lin g , us e a n o p am p t o co m p l y wi th t h e in p u t r e q u ir emen ts o f the ad9 861. th e in p u ts accep t a sig n al wi t h a 2 v p - p dif f er en t i al i n p u t swi n g ce n t er e d a b o u t one-half o f t h e s u p p ly v o l t a g e (a vdd/2) . i f t h e dc b i as is s u p p lie d exter - nal l y , t h e i n t e r n al in p u t b i as cir c ui t sh o u ld b e p o w e r e d do wn b y wr i t i n g t o r e g i s ters rx_a dc b i as [reg is ter 0x3, b i t 6] a nd rx_b dc b i as [reg is t e r 0x4, b i t 7]. the ad cs in t h e AD9861 a r e desig n e d t o s a m p le dif f er en tial in p u t sig n als. th e dif f er en t i al i n p u t p r o v i d es i m p r o v e d n o is e imm u ni ty a nd b e t t er thd and s f d r p e r f o r ma n c e fo r t h e rx p a t h . i n sys t em s t h a t us e sin g le - e n d e d sig n als, t h es e in pu ts c a n b e dig i t i ze d , b u t i t is r e co m m e nde d t h a t a si n g l e -e n d e d - t o - dif f er en t i al co n v ersio n b e p e r f o r m e d . a sin g le- e n d e d -t o- dif f er en t i al co n v ersio n can b e p e r f o r m e d b y usin g a t r a n sfo r m e r c o upl i ng c i rc u i t ( t y p i c a l ly f o r s i g n a l s ab ove 1 0 m h z ) or by usin g a n o p er a t io nal a m p l if ier , suc h as the ad8 138 (typ ical l y fo r sig n als be lo w 10 mh z). adc volta g e references the AD9861 10 -b i t ad cs us e in t e r n al r e f e r e n c es tha t a r e desig n e d t o p r o v ide fo r a 2 v p- p dif f er en t i al in p u t ra n g e . the i n te r n a l b a n d g a p re f e re nc e ge ne r a te s a st abl e 1 v re f e re nc e l e vel a nd is de cou p le d t h r o u g h t h e v r ef p i n. ref t a nd ref b a r e t h e dif f er en t i a l r e fer e n c es g e n e ra t e d b a s e d on t h e v o l t a g e l e v e l of v r e f . f i g u re 7 2 show s t h e pr op e r d e c o upl i n g of t h e re f e r- en c e p i n s v r ef , reft , an d refb w h en usin g t h e i n t e r n al re f e re nc e . d e c o upl i ng c a p a c i tor s shou l d b e pl a c e d a s cl o s e to t h e re f e re nc e pi ns a s p o ss i b l e . e x t e r n al r e fer e n c es reft and r e fb a r e cen t er e d a t a v dd/2 wi t h a dif f er en t i al v o l t a g e e q ual t o t h e v o l t a g e a t vref (b y defa u l t 1 v w h e n usin g t h e in t e r n al r e fer e n c e), al lo win g a p e ak- t o -p e a k dif f er en t i al v o l t a g e s w i n g o f 2 vref . f o r exa m ple , t h e defa u l t 1 v vre f r e fer e n c e acce p t s a 2 v p-p dif f er en t i al i n p u t swi n g and t h e of fs et v o l t a g e sh ou ld b e reft = a v d d /2 + 0.5 v refb = a v d d /2 C 0.5 v 03606-0-020 0.1 f 0.1 f 10 f 0.1 f 0.1 f vref AD9861 0.5v to adcs reft refb 10 f f i g u re 72. t y pic a l r x p a t h d ecoupl i ng an ext e r n al r e fer e n c e ma y b e us e d fo r sys t em s t h a t r e q u ir e a dif f er en t i n p u t v o l t a g e ra n g e , hig h acc u rac y ga i n ma t c hi n g b e tw e e n m u l t i p le de vices, o r im p r o v em en t s in tem p e r a t u r e dr if t a nd n o is e cha r ac t e r i s t ics. w h en a n ext e r n al r e fer e n c e is desir e d , t h e i n ter n a l rx b a nd ga p r e fer e n c e m u st b e p o w e r e d do w n usin g t h e v r ef2 r e g i s t er [reg ist e r 0x5, b i t 4] a nd t h e ext e r n al r e fer e n c e dr iving t h e v o l t a g e l e ve l o n t h e v r ef p i n. th e ext e r n al v o l t a g e lev e l sh o u ld be o n e-half o f th e desir e d p e a k -t o- p e ak dif f er en t i a l v o l t a g e s w i n g. the r e s u l t is t h a t t h e dif f er en t i al v o l t a g e r e fer e n c es a r e dr i v en t o ne w v o l t a g es: reft = a v d d /2 + v ref /2 v refb = a v d d /2 C v ref /2 v i f a n ext e r n al r e fer e n c e is us e d , i t is r e co mm e nde d n o t t o exce e d a dif f er en t i al o f fs et v o l t a g e fo r t h e r e fer e nce g r e a t e r t h an 1 v . c l ock i n p u t a n d c o ns id er at ions t y p i cal h i g h s p eed a d c s us e b o th c l oc k e d g e s t o g e n e ra t e a va r i ety o f in t e r n al timing sig n als a n d , as a r e s u l t , ma y be s e n s i t i v e t o clo c k d u ty c y cle . c o mm only , a 5% tolera n c e is r e q u ir e d o n t h e clo c k d u ty c y cle t o ma in t a i n d y na mic p e r f o r m- anc e ch ar a c te r i s t i c s . t h e a d 9 8 6 1 c o n t ai ns cl o c k d u t y c y cl e s t a b i l i z er cir c ui t r y (d cs). th e d c s r e t i m e s t h e in ter nal ad c c l oc k (n o n sa m p li n g ed g e ) a n d p r o v i d e s th e a d c wi th a n o minal 50 % d u ty c y cle . i n p u t clo c k ra t e s o f o v er 40 mh z c a n u s e t h e d c s s o t h a t a wide ra n g e o f in p u t clock d u ty c y cles ca n b e a c c o m m o d a t e d . c o n v e r s e l y , d c s s h o u l d n o t b e u s e d f o r r x s a m p ling b e lo w 40 ms ps. m a in ta inin g a 50 % d u ty c y c l e c l o c k is p a r t ic u l a r ly im p o r t a n t i n hig h sp e e d a p plic a t ion s w h e n p r o p er s a m p le- a n d -h ol d t i m e s fo r t h e c o n v er t e r a r e r e quir e d t o m a i n ta in h i g h p e rf o r m a n c e . t h e d c s ca n be en a b led b y w r i t in g hig h s t o t h e rx _a/rx_b clk d u ty r e g i st er b i t s [reg is ter 0x06/0x07, b i t 4]. the d u ty c y cle s t a b i l izer us es a de l a y-lo ck e d lo o p t o cr e a t e t h e nons am pl i n g e d ge. a s a re su lt , a n y ch ange s to t h e s a m p l i ng f r e q u e nc y re qu i r e a ppro x i m a t el y 2 s to 3 s to a l l o w t h e dl l to adj u st to t h e ne w r a te and s e tt l e . h i g h s p e e d, hi g h re s o lut i on ad cs a r e s e n s i t i v e t o t h e q u ali t y o f t h e clo c k i n p u t. th e
AD9861 rev. 0 | page 24 of 52 degradation in snr at a given full-scale input frequency (f input ), due only to aperture jitter (t a ), can be calculated with the following equation: snr degradation = 20 log [(?) f in t a )] in the equation, the rms aperture jitter, t a , represents the root- sum-square of all jitter sources, which includes the clock input, analog input signal, and adc aperture jitter specification. undersampling applications are particularly sensitive to jitter. the clock input is a digital signal that should be treated as an analog signal with logic level threshold voltages, especially in cases where aperture jitter may affect the dynamic range of the AD9861. power supplies for clock drivers should be separated from the adc output driver supplies to avoid modulating the clock signal with digital noise. low jitter crystal-controlled oscillators make the best clock sources. if the clock is generated from another type of source (by gating, dividing, or other meth- ods), it should be retimed by the original clock at the last step. power dissipation and standby mode the power dissipation of the AD9861 rx path is proportional to its sampling rate. the rx path portion of the digital (drvdd) power dissipation is determined primarily by the strength of the digital drivers and the load on each output bit. the digital drive current can be calculated by i drvdd = v drvdd c load f clock n where n is the number of bits changing and c load is the average load on the digital pins that changed. the analog circuitry is optimally biased so that each speed grade provides excellent performance while affording reduced power consumption. each speed grade dissipates a baseline power at low sample rates, which increases with clock frequency. the baseline power dissipation for either speed grade can be reduced by asserting the adc_lo_pwr pin, which reduces internal adc bias currents by half, in some case resulting in degraded performance. to further reduce power consumption of the adc, the adc_lo_pwr pin can be combined with a serial programmable register setting to configure an ultralow power mode. the ultralow power mode reduces the power consumption by a fourth of the normal power consumption. the ultralow power mode can be used at slower sampling frequencies or if reduced performance is acceptable. to configure the ultralow power mode, assert the adc_lo_pwr pin and write the following register settings: register 0x08 (msb) 0000 1100 register 0x09 (msb) 0111 0000 register 0x0a (msb) 0111 0000 either of the adcs in the ad9 861 rx path can be placed in standby mode independently by writing to the appropriate spi register bits in registers 3, 4, and 5. the minimum standby power is achieved when both channels are placed in full power- down mode using the appropriate spi register bits in registers 3, 4, and 5. under this condition, the internal references are powered down. when either or both of the channel paths are enabled after a power-down, the wake-up time is directly related to the recharging of the reft and refb decoupling capacitors and the duration of the power-down. typically, it takes approxi- mately 5 ms to restore full operation with fully discharged 0.1 f and 10 f decoupling capacitors on reft and refb. tx path block the AD9861 transmit (tx) path includes dual interpolating 10-bit current output dacs that can be operated independently or can be coupled to form a complex spectrum in an image reject transmit architecture. each channel includes two fir filters, making the AD9861 capable of 1, 2, or 4 interpola- tion. high speed input and output data rates can be achieved within the limitations of table 9. table 9. AD9861 tx path maximum data rate interpolation rate 20-bit interface mode input data rate per channel (msps) dac sampling rate (msps) fd, hd10, clone 80 80 1 hd20 160 160 fd, hd10, clone 80 160 2 hd20 80 160 fd, hd10, clone 50 200 4 hd20 50 200 by using the dual dac outputs to form a complex signal, an external analog quadrature modulator, such as the analog devices ad8349, can enable an image rejection architecture. (note: the AD9861 evaluation board includes a quadrature modulator in the tx path that accommodates the ad8345, ad8346 and the ad8345 footprints.) to optimize the image rejection capability, as well as lo feedthrough suppression in this architecture, the AD9861 offers programmable (via the spi port) fine (trim) gain and offset adjustment for each dac. also included in the AD9861 are a phase-locked loop (pll) clock multiplier and a 1.2 v band gap voltage reference. with the pll enabled, a clock applied to the clkin input is multi- plied internally and generates all necessary internal synchronization clocks. each 10-bit dac provides two complementary current outputs whose full-scale currents can be determined from a single external resistor. an external pin, txpwrdwn, can be used to power down the tx path, when not used, to optimize system power consumption. using the txpwrdwn pin disables clocks and some analog circuitry, saving both digital and analog power. the power-down mode leaves the biases enabled to facilitate a quick recovery time, typically <10 s. additionally, a sleep mode is available, which turns off the dac output current, but leaves all other circuits active, for a modest power savings. an spi compliant serial port is used to program the many features of the AD9861. note that in power-down mode, the spi port is still active.
AD9861 rev. 0 | page 25 of 52 dac equ i va lent circu i ts the AD9861 tx p a th co n s is t i n g o f d u al 10-b i t d a cs is sh o w n in f i gur e 73. the d a cs i n teg ra te a hig h p e r f o r ma nce tx d a c c ore, a pro g r a m m a bl e g a i n c o n t ro l t h rou g h a pro g r a m m a bl e ga in am plif ier ( t xpga), co a r s e ga in co n t r o l, a nd o f fs et a d j u s t - men t and f i ne g a in con t r o l t o co m p e n s a t e fo r syst e m mis m a t ches . c o a r s e ga in a p plies a g r os s s c ali n g t o ei t h er d a c b y 1, (1/2), or ( 1 / 1 1 ) . t h e t x p g a prov i d e s g a i n c o n t ro l f r om 0 d b to C20 db in s t eps o f 0.1 db a nd is co n t r o l l ed via t h e 8-b i t txpga s e t t in g. a f i ne ga in ad j u s t m e n t o f 4% f o r eac h c h a n n e l is co n - t r ol le d t h r o u g h a 6-b i t f i n e gain r e g i s t er . b y defa u l t, co a r s e ga i n is 1, t h e txpg a is s et t o 0 db , a nd t h e f i n e ga i n is s et t o 0 % . the tx d a c co re o f t h e ad986 1 p r o v ides d u al, dif f er en t i al, co m p le m e n t a r y c u r r en t o u t p u t s g e n e r a t e d f r o m t h e 10- b i t da t a . the 10-b i t d u al d a cs s u p p o r t u p da te ra t e s u p t o 200 ms ps. the dif f er en t i al o u t p uts (i o u t+ a nd i o ut C) o f e a ch d u al d a c are c o m p l e me n t ar y , me an i n g t h a t t h e y a l w a y s a d d up to t h e fu ll- s c ale c u r r e n t o u t p ut o f t h e d a c, i ou t f s . o p t i m u m a c p e r f o r m a n c e lo ads o r a t r a n sfo r m e r . 03606-0-004 reference bias iout+a pga iout? a + + + + txdac offset dac iout+b pga iout? b + + + + txdac offset dac f i gure 73. t x d a c o u tput struc t ur e bl o c k d i agr a m t h e f i ne g a i n c o n t ro l prov i d e s i m prove d b a l a nc e of q a m m o d u l a t e d sig n a l s, r e su l t in g in im p r o v e d m o d u la t i on acc u rac y a nd im a g e r e j e c t io n. the i n de p e n d e n t d a c a and d a c b o f fs et co n t r o l adds a smal l dc c u r r en t t o ei t h er io ut+ o r io ut C (n ot b o t h ). the s e le c t ion of w h i c h iou t t h i s of f s e t c u r r en t i s d i re c t e d tow a rd i s p r og ra mma b l e v i a r e g i st er s e t t i n g. of fs et co n t rol ca n b e us e d fo r s u p p r es sio n o f a n l o le aka g e sig n al t h a t typical l y r e s u l t s a t th e o u t p u t o f the m o d u l a t o r . i f th e AD9861 is dc-co u p l ed t o an e x te r n a l mo d u l a tor , t h i s fe a t u r e c a n b e u s e d to c a nc el t h e out p ut o f fs et on t h e AD9861 as we l l as t h e in p u t o f fs et on t h e m o d u l a t o r . t h e re f e re nc e c i rc u i t r y i s show n i n f i g u re 7 4 . 03606-0-005 dac a and dac b reference biases fsadj refio 0.1 fr set 4k ? current source array i outfsmax i ref 1.2v reference f i gure 74. r e ference ci r c u i tr y r e f e rri n g t o th e tra n s f e r fun c ti o n o f th e f o llo w in g eq ua ti o n , i ou tf s m a x is t h e maxim u m c u r r en t o u t p ut o f t h e d a c wi t h t h e defa u l t gain s e t t in g ( 0 db) , an d i s b a s e d o n a r e fer e n c e c u r r en t, i ref . i ref is s et b y t h e i n t e r n al 1.2 v r e fer e n c e and t h e ext e r n al r set re s i stor . i ou t f sm a x = 64 ( refi o/r set ) ty p i c a l l y , r set is 4 k?, w h ich s e t s i ou tf s m a x t o 20 ma, t h e o p ti m a l d y n a m i c se t t in g f o r th e t x d a c s . i n cr eas i n g r set by a f a c t or of 2 prop or t i on a l ly d e c r e a s e s i ou t f sma x b y a fac t o r o f 2. i ou tf s m a x o f ea c h d a c ca n b e r e scaled ei t h e r s i m u l t a n eo us l y usin g t h e txpg a ga in r e g i st er o r in de p e n d e n t l y usin g t h e d a c a / d a c b co a r s e ga in r e g i s t ers. t h e t x p g a f u n c t i on prov i d e s 2 0 d b of s i m u lt a n e o u s g a i n ra n g e fo r b o t h d a cs, an d is con t r o l l e d b y wr i t in g t o t h e s p i r e gis t er t x pga ga in f o r a p r ogra m m a b l e f u ll-scale o u t p u t o f 10% t o 100% o f i ou tf s m a x . th e g a in c u r v e is li n e a r in d b , w i t h s t eps o f a b o u t 0. 1 db . i n t e r n al ly , t h e ga i n is con t r o l l e d b y cha n g i n g t h e ma in d a c b i as c u r r en ts wi t h an in t e r n al txpga d a c w h os e o u t p u t is h e a v i l y f i lt er e d vi a an o n - c hi p r - c f i l t er t o p r o v i d e co n t in uo us g a i n tra n s i ti o n s . n o t e th a t th e se t t lin g ti m e a n d ba n d w i d t h o f t h e t x pga d a c ca n be im p r o v ed b y a f a c t or of 2 by w r it i n g to t h e t x p g a f a s t re g i ste r . e a c h d a c has in dep e n d en t co ar s e ga in co n t r o l . c o a r s e ga in co n t r o l can b e us e d t o accommo d a t e dif f er en t i ou tf s f rom t h e d u al d a cs. th e co a r s e f u l l -s cal e o u t p u t co n t r o l ca n be ad j u s t ed b y usin g th e d a c a/d a c b co ars e ga in r e g i st ers t o 1/2 o r 1/11 o f t h e n o mina l f u l l -s cale c u r r en t. f i ne ga in con t rols a n d dc o f fs et co n t r o ls ca n b e us e d to co m p en s a t e f o r misma t ch es (f o r sys t em l e v e l cal i b r a t ion), a l l o w i ng i m prove d m a tch i ng c h ar a c te r i st i c s of t h e t w o t x ch an nel s a n d ai d i ng i n suppre s s i ng lo fe e d t h rou g h . t h i s i s es p e c i al ly us ef u l in ima g e r e je c t io n a r chi t e c t u r e s. th e 10 -b i t dc of f s e t c o n t ro l of e a ch d a c c a n b e u s e d i n d e p e nd e n t l y to prov i d e a n of f s e t of up to 1 2 % of i out f sma x t o ei t h er dif f er en t i al p i n, th us al lo win g calib r a t io n o f a n y sys t em o f fs ets. th e f i n e g a i n co n t r o l wi th 5-b i t r e so l u ti o n allo w s th e i ou t f sma x of e a ch d a c t o be va r i e d o v er a 4% ran g e , al lo win g co m p en s a tio n o f a n y d a c o r sys t em ga i n misma t ch es. f i ne ga in co n t r o l is s et t h r o u g h t h e d a c a/ d a c b f i ne ga in r e g i st ers, a nd t h e o f fs et c o n t r o l o f e a c h da c i s a c c o m p l i s h e d u s i n g t h e da c a / da c b o f fs et r e g i s t ers.
AD9861 rev. 0 | page 26 of 52 clock input configuration the quality of the clock and data input signals is important in achieving optimum performance. the external clock driver circuitry provides the AD9861 with a low jitter clock input that meets the min/max logic levels while providing fast edges. when a driver is used to buffer the clock input, it should be placed very close to the AD9861 clock input, thereby negating any transmission line effects such as reflections due to mismatch. programmable pll clkin can function either as an input data rate clock (pll enabled) or as a dac data rate clock (pll disabled). the pll clock multiplier and distribution circuitry produce the necessary internal timing to synchronize the rising edge trig- gered latches for the enabled interpolation filters and dacs. this circuitry consists of a phase detector, charge pump, voltage controlled oscillator (vco), and clock distribution block, all under spi port control. the charge pump, phase detector, and vco are powered from pll_avdd, while the clock distribu- tion circuits are powered from the dvdd supply. to ensure optimum phase noise performance from the pll clock multiplier circuits, pll_avdd should originate from a clean analog supply. the speed of the vco within the pll also has an effect on phase noise. the pll locks with vco speeds as low as 32 mhz up to 350 mhz, but optimal phase noise with respect to vco speed is achieved by running it in the range of 64 mhz to 200 mhz. power dissipation the AD9861 tx path power is derived from three voltage supplies: avdd, dvdd, and drvdd. idrvdd and idvdd are very dependent on the input data rate, the interpolation rate, and the activation of the internal digital modulator. iavdd has the same type of sensitivity to data, interpolation rate, and the modulator function, but to a much lesser degree (< 10%). sleep/power-down modes the AD9861 provides multiple methods for programming power saving modes. the externally controlled txpwrdwn or spi programmed sleep mode and full power-down mode are the main options. txpwrdwn is used to disable all clocks and much of the analog circuitry in the tx path when asserted. in this mode, the biases remain active, therefore reducing the time required for re-enabling the tx path. the time of recovery from power- down for this mode is typically less than 10 s. the sleep mode, when activated, turns off the dac output currents, but the rest of the chip remains functioning. when coming out of sleep mode, the AD9861 immediately returns to full operation. a full power-down mode can be enabled through the spi register, which turns off all tx path related analog and digital circuitry in the AD9861. when returning from full power-down mode, enough clock cycles must be allowed to flush the digital filters of random data acquired during the power-down cycle. interpolation stage interpolation filters are available for use in the AD9861 transmit path, providing 1 (bypassed), 2, or 4 interpolation. the interpolation filters effectively increase the tx data rate while suppressing the original images. the interpolation filters digitally shift the worst-case image further away from the desired signal, thus reducing the requirements on the analog output reconstruction filter. there are two 2 interpolation filters available in the tx path. an interpolation rate of 4 is achieved using both interpolation filters; an interpolation rate of 2 is achieved by enabling only the first 2 interpolation filter. the first interpolation filter provides 2 interpolation using a 39-tap filter. it suppresses out-of-band signals by 60 db or more and has a flat pass-band response (less than 0.1 db ripple) extending to 38% of the input tx data rate (19% of the dac update rate, f dac ). the maximum input data rate is 80 msps per channel when using 2 interpolation. the second interpolation filter provides an additional 2 interpola- tion for an overall 4 interpolation. the second filter is a 15-tap filter, which suppresses out-of-band signals by 60 db or more. the flat pass-band response (less than 0.1 db attenuation) is 38% of the tx input data rate (9.5% of f dac ). the maximum input data rate per channel is 50 msps per channel when using 4 interpolation. latch/demultiplexer data for the dual-channel tx path can be latched in parallel through two ports in half-duplex operations (hd20 mode) or through a single port by interleaving the data (fd, hd10, and clone modes). see the flexible i/o interface options section in the digital block description and the clock distribution block section for further descriptions of each mode.
AD9861 rev. 0 | page 27 of 52 auxiliary converters the AD9861 contains auxiliary analog-to-digital converters (auxadcs) and auxiliary digital-to-analog converters (auxdacs). these auxiliary converters can be used to measure or force system-wide control signals. by default, the auxiliary converters are disabled and powered down. enabling and controlling the auxiliary converters is achieved through the serial programmable registers. pins 29, 30, and 46 are configurable either as auxdac outputs or as auxadc inputs. the respective auxadc inputs are connected to the external pin when a conversion is initiated and are disconnected when the conversion is complete. the auxdac outputs are enabled by writing to the respective power-up registers in register 0x29. ? pin 29 can be connected to auxdac_a and/or auxadc_a channel 2. ? pin 30 can be connected to auxdac_b and/or auxadc_a channel 1. ? pin 46 can be connected to auxdac_c and/or auxadc_b. auxiliary dacs the AD9861 integrates three 8-bit voltage output auxiliary digital-to-analog converters (auxdacs), which can be used for supplying various control voltages throughout the system such as a vcxo voltage control or external vga gain control. the auxdacs have a programmable full-scale output voltage, v outfs , and can be synchronized to update with a single register write or a rising edge on the txpwrdwn pin. by default, the auxdac outputs are powered down and require a serial write to the power-up registers [register 0x29, bits 2C0] to enable them. the full-scale output of each auxdac is independently programmable to the full scales of 2.5 v, 2.7 v, 3.0 v, or 3.3 v by using serial register 0x17. the auxdac outputs have an i-to-v driver that produces a voltage output that settles to 1 lsb within 0.5 s. the output driver is capable of sinking or sourcing up to 6 ma. using the auxdac requires the spi to be operational. the auxdacs are based on a resistor divider network. the auxdacs output level is proport ional to the straight binary input codes from the appropriate spi registers, registers 0x24 to 0x26. by default, the auxdac output is updated immediately following the register write, but the update can occur synchronously to a single register write or to the txpwrdwn rising edge. in slave mode, the auxdac update occurs when a logic high is written to the appropria te update registers [register 0x28, bits 2C0, update c, b, and a]. slave mode is enabled by writing a high to the slave mode register bit [register 0x28, bit 7, slave enable]. another synchronization mode allows any combination of auxdacs to be updated along with an externally applied rising edge to the txpwrdwn pin. typical settling time for the auxdac output is less than 0.5 s, but is dependent on the load. auxiliary adcs two auxiliary 10-bit sar analog-to-digital converters (auxadcs) are available for monitoring various external signals throughout the system, such as a receive signal strength indicator (rssi) function or temperature indicator. the auxadcs have many spi progra mmable options. register settings can be used to configure various full-scale reference options, change the sampling ra te, and average multiple sample readings. by default, the auxadc start conversion and output value is accessed through the register map. additionally an auxiliary serial port can be enabled and used to initiate a conversion and read back the auxadc data. the auxiliary serial port interface is available so that the normal spi can be used to program other options while the auxadc is accessed. by default, the auxadcs are powered down and automatically powered up when a conversion is initiated. the two auxadcs (auxadc_a and auxadc_b) can monitor up to three system signals. auxadc_a has multi- plexed inputs that control whether pin aux_adc_a1 or pin aux_adc_a2 is connected to the input of auxadc_a. the multiplexer is programmed thro ugh register 0x22, bit 1, selecta. by default, the register is low, which connects the aux_adc_a2 pin to the input. the full-scale auxadc reference can be generated from the analog supply (supply dependent), an internal reference, or from an external applied reference. table 10 shows the register settings required to select the auxadc full-scale reference. by default, an internal reference provides a buffered full-scale reference for both of the auxadcs, which is equal to the supply voltage for the auxadcs (pll_avdd). a supply independent 2.5 v or 3.0 v internal full-scale reference can be enabled by writing to register auxadc ref enable and auxadc ref fs in register 0x17. this internal reference is based on the main rx path adc vref voltage, so it requires the main rx path vref to be enabled. another auxadc full-scale refere nce option is an externally supplied full-scale reference. the external reference can be applied to either or both of the auxadcs by setting the appropriate bit(s) in registers 0x22 and 0x17. setting either or both of these bits high disconnects the internal reference buffer and enables the externally applied reference from the auxadc_ref pin to the respective channel(s).
AD9861 rev. 0 | page 28 of 52 table 10. co nfi g uring auxad c refer e nce auxadc_a r e f e rence configuration auxad c ref en able [register 0x17, bit 1] auxad c ref fs [register 0x17, bit 0] refsel a/b [register 0x22, bit 2/bit 5] no tes b u f f e r e d pll_ v d d 0 0 0 d e f a u l t m o d e . internal 3.0 v (3 x vref) 1 0 1 decouple at auxadc_ref pin. vref voltage from rx path. internal 2.5 v (2. 5 x vref) 1 1 1 decouple at auxadc_ref pin. externally force d 0 don't care 1 force and decouple at auxadc_ref pin. the auxad c s can convert at rates of up to 5.3 3 msps (0.1875 s maximum co nvers i on time) and have a bandwidth of around 200 khz. the co nver si on time, inclu d ing setup, requires 12 clock cycles. the maximu m clock r a te for the aux a dcs is 64 mhz a nd is ge n e r a te d fr o m a di vid e d do w n rx adc clo c k. t h e div i d e do w n r a tio is con t rolled by register auxadc c l ock div [reg ister 0 x 23, bits 1, 0]. by default, the r x adc clock is di vided by 4. at an rx ad c rate greater t h an 64 mhz, t h e aux a dc clock d i v r e gister must be set to divi de -by - 2 o r divi de- b y - 4 . on-c hi p a v era g in g o f 2, 4, 8, 16, 32, o r 64 s a m p les ca n be e n abl e d t h rou g h r e g i ste r 0 x 1 8 f o r a u x a d c _ a or t h rou g h reg i st er 0x19 fo r a u xad c _b . w h en t h e a v erag in g o p t i on is ena b le d , t h e a u xad c co n t in ua l l y co n v er ts t h e n u m b er o f s a m p les s p e c if ie d an d o u t p u t s t h e a v era g e val u e . there are t h ree modes of operat ing the auxad c : s p i o p er a t ion m o de (def a u l t ), s p i wi t h ext e r n al s t a r t con v er t o p era t ion m o de, a nd a u x _ spi o p er a t ion m o de. i n t h e def a u l t sp i o p era t ion mo de , a conv ersio n is i n i t i a te d by writi n g a log i c hig h to one or b o th of the s t art register b i ts, start a or start b [register 0x2 2 , bit 0 or bit 3] . if auxadc i s configured as averagi n g mode, th e proper start bit is the start averag e auxa dc a/b re gist er [register 0x18, bit 7/r e gis ter 0x19, bit 7]. when t h e conv ersion is co mpl ete, t h e str a ig ht binary, 10-b i t output data of t h e auxa dc i s writte n to one of three reserv ed locations in the register map, de pending on w h i c h auxad c an d w h ic h mul t iplexed inpu t is selecte d . bec a us e the auxad c s output 10 bit s, t w o register addresses are nee d e d for each dat a location. in the optional s p i wi t h ext e r n al s t a r t con v er t o p era t ion m o de, the conversio n i s initi a te d by as ser t in g aux s pi _csb, a nd da ta retriev a l is accomplis h e d throu gh the spi i n ter face (data retriev a l is s i mil a r to the defa ult operation). the auxspi_csb can b e configur ed to i n i t iate t h e conversio n of eit h er one of the auxadcs. this mode is config ured by set t i n g the a u xspi enable reg i ster bit [reg ist e r 0x22, bit 7]. an optio n al au xiliary seri al port int e rface (au x spi) can be us ed t o a cce ss an a u xa d c . t h e a u xspi ca n in it ia te a n a u xa dc co nver sio n a nd can b e use d to retriev e the dat a . the auxspi can b e co nfigur ed to allo w de di cate d co ntr o l o f o n e o f the auxadcs an d i s ava i la ble so t h at t h e spi is not conti n ually busy retriev i ng auxadc data. the auxspi can be e n able d and co nfigure d by setti ng reg i ster auxspi enable [register 0x22, bit 7]. also req u ired i s that t h e n orm al serial port in terface be con f igured for 3-wire m o d e ( t h e spi_sdo pi n must be dis a ble d t o use the aux_s p i_sdo pi n) by setti ng t h e s d io bid i r regis ter bit [r egist e r 0x00, bit 7]. regis ter bi t sel bnota [reg ist e r 0x22, bit 6] configures whe t he r auxadc_ a or auxadc_ b is c o ntrolled by t h e auxspi. auxadc_ a has two i n puts: auxadc_a1 and auxadc_a2. setti ng t h e sel e ct a bi t [regis te r 0x22, bit 1] de termi nes which of the mul t iplex e d i n puts is connecte d to aux a dc_a. the auxspi consis ts of a chip select pin (aux_spi_cs, pin num b er 4) , a cl o c k pin ( a ux _ s pi_clk) , an d a d a ta o u tpu t pi n (aux _ s p i _ s do m u lti p le x with th e spi_sdo pin ) . a conv e r sion is i n it iat e d by pulsing the au x _ spi_cs pi n low (au x _spi_c s sho u l d r e mai n l o w du ri ng the e n tir e co nv ers i o n cycl e, i n clu d i n g the re adbac k phase). whe n t h e conversio n is co mplet e , the dat a pin, a u x_spi_ sdo, transi tions from a logic low to a logic hig h . at this point, the u s er su p p lies an exter nal clock on the aux_spi_cl k pin. the aux_ spi_clk p i n s h ould be t i e d low whe n not i n use. no data i s present o n the first risi ng e d ge . the data outpu t bit i s update d on the fall ing e d g e of the clock pulse a nd i s sett led by a n d ca n be la tche d o n t h e nex t clo c k rising edg e . the dat a arriv e s se r i ally, msb first. the auxspi runs at a rate u p to 16 mhz. o p era t ion o f t h e a u x_s p i r e q u i r es t h a t 3- wir e sp i m o de b e us e d , dis a b l i n g t h e sd o pin. i f t h e con t r o l l er is a 4- wir e in t e r f ace , a m e t h o d o f co nn ec tin g th e 3 - wir e AD9861 in ter face t o t h e 4- w i r e con t r o l l er is s u g g es t e d in f i gur e 75. an exa m p l e o f a n a u xs p i acces s is sh o w n in f i gur e 75. i n the a u xs pi co nf igura t io n, a st a r t con v er t is in i t ia t e d b y a p plyi n g a r i sin g edg e t o t h e a u x_s p i_cs p i n. a r i sin g e d g e o n t h e a u x _ s p i_d o pin i n d i c a tes t h a t a co n v ersio n is do ne. s u p p ly in g a clo c k t o t h e a u x_s p i_cl k t h en o u t p u t s da t a o n t h e au x _ s p i _ d o p i n , m s b f i r s t . 03606-0-006 controlle r ad986x spi_cs[x] spi_clk spi_cs spi_clk spi_sdio spi_di f i gure 75. d i agr a m to conn ec t 3- wire spi to a 4- wire s p i control l e r
AD9861 rev. 0 | page 29 of 52 f i g u r e 76 s h o w s a ti m i n g di a g ra m o f th e a u xs p i wh e n i t is us e d t o co n t r o l and acces s an a u xad c . f i g u r e 77 s h o w s th e tim i n g f o r e a c h o f th e th r e e a u xa d c m o d e s o f o p e r a t i o n . 03606-0-021 auxspi_cs 12 3 d 9 d 8 d 0 1. auxadc conversion start signal 2. auxadc conversion done 3. auxadc output udate (msb) auxspi_clk auxspi_sdo f i g u re 76. ti m i ng d i ag r a m of aux s pi 03606-0-007 t conversion = t c 16 spi clk 16 spi clk normal spi readout 8-bit serial output normal spi readout cycle time = 16 spi clk + t c + 16 spi clk external start covert bit and spi readout mode cycle time = t c + 16 spi clk readout mode with auxiliary spi cycle time = t c + 8 spi clk external start covert bit and spi readout mode readout mode with auxiliary spi external pin used to initiate a start conversion external pin used to initiate a start conversion 16 spi clks used to configure and initiate a start conversion 16 spi clks used to read back 8 register bits 16 spi clks used to read back 8 register bits f i g u re 77. aux a dc d a t a c y c l e ti mes f o r v a r i ous r e ad out m e t h ods
AD9861 rev. 0 | page 30 of 52 digi tal block the AD9861 dig i tal b l o c k al lo ws th e de vic e t o be co nf igur e d in va r i o u s t i min g a nd o p er a t io n m o de s. t h e fol l o w in g s e c t i o n s dis c us s t h e f l exi b l e i/o i n t e r f ac es, t h e clo c k dist r i b u t i on b l o c k, an d t h e pro g r a m m i ng of t h e d e v i c e t h rou g h mo d e pi ns or spi re g i ste r s . flexi b le i/o in ter f ace optio n s the AD9861 can acco mmo d a t e va r i o u s da t a in ter face tra n sf er o p tio n s (f lexi b l e i/o). th e AD9861 us es tw o 10-b i t b u s e s, an u p p e r b u s (u10) a n d a lo w e r b u s (l10), t o tra n sf er th e d u al- cha n n e l 10- b i t ad c da t a and d u al -cha nne l 10 -b i t d a c da t a b y m e a n s o f i n t e r lea v ed d a ta , pa r a lle l d a ta , o r a m i x o f b o th . t a b l e 11 s h o w s t h e dif f er en t i/ o co nf igu r a t io n s o f t h e mo des dep e ndin g o n half-d u p lex o r f u l l -d u p lex o p era t ion. t a b l e 12 a nd t a b l e 13 summa r i ze t h e p i n co nf igur a t ion s versus t h e mo des. table 11. flexi b le data interface modes mode name tx only mode ( h alf- duplex) rx o n ly mo de ( h alf- duplex) concurrent tx + rx mode (full- duplex) general notes hd20 u[0:9] digital back end AD9861 tx_a data 03606-0-008 l[0:9] tx_b data iface1 tx/rx iface2 output clock iface3 output clock l[0:9] digital back end AD9861 rx_a data 03606-0-012 rx_b data u[0:9] iface1 tx/rx iface2 output clock iface3 output clock n/a rx data rate = 1 ad c s a mpl e r a te two 1 0 -bit p a ra lle l r x d a ta buses tx data rate = 1 ad c s a mpl e r a te two 1 0 -bit p a ra lle l tx d a ta buses hd10 u[0:9] digital back end AD9861 tx_a/b data 03606-0-009 l[9] txsync iface1 tx/rx iface2 output clock iface3 output clock u[9] digital back end AD9861 rxsync 03606-0-013 rx_a/b data l[0:9] iface1 tx/rx iface2 output clock iface3 output clock n/a rx data rate = 2 ad c s a mpl e r a te one 10-bit inte rle a ved rx data bu s tx data rate = 2 ad c s a mpl e r a te one 10-bit inte rle a ved tx data bu s fd u[0:9] digital back end AD9861 tx_a/b data 03606-0-010 l[0:9] iface1 txsync iface2 output clock iface3 output clock u[0:9] digital back end AD9861 03606-0-014 rx_a/b data l[0:9] iface1 iface2 output clock iface3 output clock u[0:9] digital back end AD9861 tx_a/b data 03606-0-016 rx_a/b data l[0:9] iface1 txsync iface2 output clock iface3 output clock rx data rate = 2 ad c s a mpl e r a te one 10-bit inte rle a ved rx data bu s tx data rate = 2 ad c s a mpl e r a te one 10-bit inte rle a ved tx data bu s clone u[0:9] digital back end AD9861 tx_a/b data 03606-0-011 txsync l[9] iface1 tx/rx iface2 output clock iface3 output clock u[0:9] digital back end AD9861 rx_a data 03606-0-015 rx_b data l[0:9] iface1 tx/rx iface2 output clock iface3 output clock n/a rx data rate = 1 ad c s a mpl e r a te two 1 0 -bit p a ra lle l r x d a ta buses tx data rate = 2 ad c s a mpl e r a te one 10-bit inte rle a ved tx data bu s requir es spi inter f ace to c o nfi g u r e; si m i l a r t o a d 98 60 data interface
AD9861 rev. 0 | page 31 of 52 table 12 describes AD9861 pin function (when mode pins are used) relative to i/o mode, and for half-duplex modes whether transmitting or receiving. table 12. AD9861 pin function vs. interface mode (no spi cases) mode name u10 l10 iface1 iface2 iface3 fd interleaved tx data interl eaved rx data txsync buffere d rx clock buffered tx clock hd10 (tx/ rx = high) interleaved tx data msb = txsync others = three-state tx/ rx = tied high 10/ 20 pin control tied high buffered tx clock hd10 (tx/ rx = low) msb = rxsync others = three-state interleaved rx data tx/ rx = tied low 10/ 20 pin control tied high buffered rx clock hd20 (tx/ rx = high) tx_a data tx_b data tx/ rx = tied high 10/ 20 pin control tied low buffered tx clock hd20 (tx/ rx = low) rx_b data rx_a data tx/ rx = tied low 10/ 20 pin control tied low buffered rx clock clone mode (tx/ rx = high) clone mode not available without spi. clone mode (tx/ rx = low) clone mode not available without spi. table 13 describes AD9861 pin function (when spi programming is used) relative to flexible i/o mode, and for half-duplex modes whether transmitting or receiving. table 13. AD9861 pin function vs. interface mo de (configured through the spi registers) mode name u10 l10 iface1 iface2 iface3 fd interleaved tx data in terleaved rx data txsync buffered system clock buffered tx clock hd10, tx mode (tx/ rx = high) interleaved tx data msb = txsync others = three-state tx/ rx = tied high optional buffered system clock buffered tx clock hd10, rx mode (tx/ rx = low) msb = rxsync other = three-state interleaved tx data tx/ rx = tied low optional buffered system clock buffered rx clock hd20, tx mode (tx/ rx = high) tx_a data tx_b data tx/ rx = tied high optional buffered system clock buffered tx clock hd20, rx mode (tx/ rx = low) rx_b data rx_a data tx/ rx = tied low optional buffered system clock buffered rx clock clone mode , tx mode (tx/ rx = high) interleaved tx data msb = txsync others = three-state tx/ rx = tied high optional buffered system clock buffered tx clock clone mode , rx mode (tx/ rx = low) rx_b data rx_a data tx/ rx = tied low optional buffered system clock buffered rx clock summary of flexible i/o modes fd mode the full-duplex (fd) mode can be configured by using mode pins or with spi programming. using the spi allows additional configuration flexibility of the device. fd mode is the only mode that supports full-duplex, receive, and transmit concurrent operation. the upper 10-bit bus (u10) is used to accept interleaved tx data, and the lower 10-bit bus (l10) is used to output interleaved rx data. either the rx path or the tx path (or both) can be independently powered down using either (or both) the rxpwrdwn and txpwrdwn pins. fd mode requires interpolation of 2 or 4. the following notes provide a general description of the fd mode configuration. for more information, refer to table 16. note the following about the tx path in fd mode: ? interpolation rate of 2 or 4 can be programmed with mode pins or spi. ? max dac update rate = 200 msps. max tx input data rate = 80 msps/channel (160 msps interleaved). ? txsync is used to direct tx input data. txsync = high indicates channel tx_a data. txsync = low indicates channel tx_b data.
AD9861 rev. 0 | page 32 of 52 ? buffered tx clock output (from iface3 pin) equals 2 the dac update rate; one rising edge per interleaved tx sample. note the following about the rx path in fd mode: ? adc clk div register can be used to divide down the clock driving the adc, which accepts up to 50 mhz (AD9861-50) or up to 80 mhz (AD9861-80). ? max adc sampling rate = 50 msps (AD9861-50) or 80 msps (AD9861-80). ? the rx path output data rate is 2 the adc sample rate (interleaved). ? rx_a output when iface2 logic level = low. rx_b output when iface2 logic level = high. hd10 mode the half-duplex, 10-bit interleaved outputs mode, hd10 can be configured using mode pins or the spi. hd10 mode supports half-duplex only operations and can interface to a single 10-bit data bus with independent rx and tx synchronization pins (rxsync and txsync). both the u10 and l10 buses are used on the AD9861, but the logic level of the tx/ rx selector (controlled through iface1 pin) is used to disable and three-state the unused bus, allowing u10 and l10 to be tied together. the msb of the unused bus acts as the rxsync (during rx operation) or txsync (during tx operation). a single pin is used to output the clocks for rx and tx data latching (from the iface3 pin) switching, depending on which path is enabled. hd10 mode requires interpolation of 2 or 4. the following notes provide a general description of the hd10 mode configuration. for more information, refer to table 16. note the following about the tx path in hd10 mode: ? interpolation rate of 2 or 4 can be programmed with mode pins or spi. ? interleaved tx data accepted on u10 bus, l10 bus msb acts as txsync. ? max dac update rate = 200 msps. max tx input data rate = 80 msps/channel (160 msps interleaved). ? txsync is used to direct tx input data. txsync = high indicates channel tx_a data. txsync = low indicates channel tx_b data. note the following about the rx path in hd10 mode: ? adc clk div register can be used to divide down the clock driving the adc, which accepts up to 50 mhz (AD9861-50) or up to 80 mhz (AD9861-80). ? max adc sampling rate = 50 msps (AD9861-50) or 80 msps (AD9861-80). ? output data rate = 2 adc sample rate. ? interleaved rx data output from l10 bus. ? rx_a output when iface2 (or rxsync) logic level = low. rx_b output when iface2 (or rxsync) logic level = high. hd20 mode the half-duplex 20-bit parallel output, hd20, can be configured using mode pins or through spi programming. hd20 mode supports half-duplex only operations and can interface to a single 20-bit data bus (two parallel 10-bit buses). both the u10 and l10 buses are used on the AD9861. the logic level of the tx/ rx selector (controlled through iface1 pin) is used to configure the buses as rx outputs (during rx operation) or as tx inputs (during tx operation). a single pin is used to output the clocks for rx and tx data latching (from the iface3 pin) switching, depending on which path is enabled. the following notes provide a general description of the hd20 mode configuration. for more information, refer to table 16. note the following about the tx path in hd20 mode: ? interpolation rate of 1, 2, or 4 can be programmed with mode pins or spi. ? max dac update rate = 200 msps. max tx input data rate = 160 msps/channel with bypassed interpolation filters, 100 msps for 2 interpolation or 50 msps for 4 interpolation. ? tx_a dac data is accepted from the u10 bus; tx_b dac data is accepted from the l10 bus. note the following about the rx path in hd20 mode: ? adc clk div register can be used to divide down the clock driving the adc, which accepts up to 50 mhz (AD9861-50) or up to 80 mhz (AD9861-80). ? max adc sampling rate = 50 msps (AD9861-50) or 80 msps (AD9861-80). ? the rx_a output data is output on l10 bus; the rx_b output data is output on u10 bus. clone mode an interface mode provides a similar interface to the ad9860 when used in half-duplex mode. this mode is referred to as clone mode and requires spi to configure. clone mode provides a parallel rx data output (20 bits) while in rx mode, and accepts interleaved tx data (10-bit) while in tx
AD9861 rev. 0 | page 33 of 52 mode. both the u10 and l10 buses are used on the AD9861. the logic level of the tx/ rx selector (controlled through the iface1 pin) is used to configure the buses for rx outputs (during rx operation) or as tx inputs (during tx operation). a single pin is used to output the clocks for rx and tx data latching (from the iface3 pin), depending on which path is enabled. clone mode requires interpolation of 2 or 4. the following notes provide a general description of the clone mode configuration. for more information, refer to table 16. note the following about the tx path in clone mode: ? interpolation rate of 2 or 4 can be programmed with mode pins or spi. ? max dac update rate = 200 msps. max tx input data rate = 80 msps/channel (160 msps interleaved). ? txsync is used to direct tx input data. txsync = high indicates channel tx_a data. txsync = low indicates channel tx_b data. ? buffered tx clock output (from iface3 pin) uses one rising edge per interleaved tx sample. note the following about the rx path in clone mode: ? adc clk div register can be used to divide down the clock driving the adc, which accepts up to 50 mhz (AD9861-50) or up to 80 mhz (ad9851-80). ? max adc sampling rate = 50 msps (AD9861-50) or 80 msps (AD9861-80). ? output data rate = adc sample rate, that is, two 10-bit parallel outputs per one buffer rx clock output cycle. ? the rx_a output data is output on l10 bus; the rx_b output data is output on u10 bus. configuring with mode pins the flexible interface can be configured with or without the spi, although more options and flexibility are available when using the spi to program the AD9861. mode pins can be used to power down sections of the device, reduce overall power consump- tion, configure the flexible i/o interface, and program the interpolation setting. the spi register map, which provides many more options, is discussed in the configuring with spi section. mode p i ns/power-up configuration options various options are configurable at power-up through mode pins, and also through control pins for power-down modes. the logic value of the configuration mode pins are latched when the device is brought out of reset (rising edge of reset ). the mode pin names and their functions are shown in table 14. table 15 provides a detailed description of the mode pins. table 14. mode pin names and functions pin name duration function rxpwrdwn permanent when high, digital clocks to rx block are disa bled. analog circuitry that require <10 s to power up are powered off. txpwrdwn permanent when high, digital clocks to tx block are disabled (pll remains powered to maintain output clock with an optional spi shut off). anal og circuitry that require <10 s to power up are powered off. tx/ rx (iface1) permanent only for hd flex i/o interface when high, digital clocks to tx block are disabled (pll remains powered to maintain output clock with an optional spi shutoff). tx analog blocks remain powered up unless tx_pwrdwn is asserted. when low, digital clocks to rx block are disa bled. rx analog circuitry remain powered up unless rx_pwrdwn is asserted. adc_lo_pwr defined at reset or power-up when enabled, this bit scales the adc power-down by 40%. spi_bus_enable (spi_cs) defined at reset or power-up this function is controlled th rough the spi_cs pin. this pin must remain low to maintain mode pin functionality (the spi port remains no nfunctional). this pin must be high when coming out of reset to enable the spi. fd/ hd defined at reset or power-up configures the flex i/o for fd or hd mode. this control applies only if the spi bus is disabled. 10/ 20 only valid for hd mode defined at reset or power-up if the flex i/o bus is in hd mode, this bit is used to configure para llel or interleaved data mode. this control applies only if the spi bus is disabled. interp0 and interp1 defined at reset or power-up the interp1 and interp0 bits co nfigure the pll and the interpol ation rate to 1 [00], 2 [01], or 4 [10]. this control applies only if the spi bus is disabled.
AD9861 rev. 0 | page 34 of 52 table 15. mode pin names and descriptions pin name description adc_lo_pwr adc low power mode option. adc_lo_pwr is latched during the rising edge of reset . logic low results in adc operation at nominal power mode. logic high results in adc consuming 40% less power than the nominal power mode. fd/ hd (sdo) for flex i/o configuration, this contro l applies only if the spi bus is disabled. fd/ hd (sdo) is latched during the rising edge of reset . logic low identifies that the dut flex i/o por t will be configured for half-duplex operation. 10/ 20 (iface2) is also latched during the rising edge of reset to identify interleaved da ta mode or parallel data modes. logic low indicates that the flex i/o will configure itself for parallel data mode. logic high indicates that the flex i/o will configure itself for interleaved data mode. 10/ 20 for flex i/o configuration, the 10/ 20 pin control applies only if the spi bus is disabled and the device is configured for hd mode. 10/ 20 is latched during the rising edge of reset . 10/ 20 (iface2) is used to identify interlea ved data mode or pa rallel data modes. logic low indicates that the flex i/o will configure itself for hd20 mode. logic high indicates that the flex i/ o will configure itself for hd10 mode. spi_bus_enable (spi_cs) spi_cs is latched during the rising edge of reset . logic low results in the spi being disabled and spi_dio, spi_clk and spi_sdo act as mode pins. logic high results in the spi being fully operati onal, and some of the mode pins are disabled. interp0 and interp1 interpolation/pll factor configuration. this co ntrol applies only if the spi bus is disabled. spi_dio (interp1) and spi_clk (interp0) configure the tx pa th for 1 [00], 2 [01], or 4 [10] interpolation and also enable the pll of the same multiplication factor. rxpwrdwn power-down control. rxpwrdwn logic level controls the power-down function of the rx path. logic low results in the rx path operating at normal power levels. logic high disables the adc clock and disables so me bias circuitry to re duce power consumption. txpwrdwn power-down control. txpwrdwn logic level controls the power-down function of the tx path. logic low results in the tx path operating at normal power levels. logic high disables the dac clocks and disables so me bias circuitry to reduce power consumption. tx/ rx power-down control. tx/ rx pin enables the appropriate tx or rx path in the half-duplex mode. a logic low disables the tx digital clock and the i/ o bus is configured as an output or three-stated. a logic high disables the rx digi tal clocks and the i/o bus is conf igured as high impedance inputs.
AD9861 rev. 0 | page 35 of 52 configuring with spi the flexible interface can be configured with register settings. using the register allows more device programmability. table 1 6 shows the required register writes to configure the AD9861 for fd, optional fd, hd20, optional hd20, hd10, optional hd10, and clone mode. note that for modes that use interleaved data buses, enabling 2 or 4 interpolation is required. table 16. registers for configuring spi register address setting description fd, mode 1 register 0x01 [7:5] [000]; clk_ modeconfigures timing mode. register 0x14 [4] high spifdnhdconfigures fd mode. register 0x14 [2] high spib 10n20configures fd mode. register 0x13 [1:0] [01] or [10] interpolation controlconfigures 2 or 4 interpolation. optional fd, mode 2 register 0x01 [7:5] [001] clk_ modeconfigures timing mode. register 0x14 [4] high spifdnhdconfigures fd mode. register 0x14 [2] high spib 10n20configures fd mode. register 0x13 [1:0] [01] or [10] interpolation controlconfigures 2 or 4 interpolation. hd20, mode 4 register 0x01 [7:5] [000]; clk_ modeconfigures timing mode. register 0x14 [4] low spifdnhdconfigures hd mode. register 0x14 [2] low spib 10n20configures hd20 mode. register 0x13 [1:0] [00], [01] or [10] interpolation controlconfigur es 1, 2, or 4 interpolation. optional hd20, mode 5 register 0x01 [7:5] [011] clk_ modeconfigures timing mode. register 0x14 [4] low spifdnhdconfigures hd mode. register 0x14 [2] low spib 10n20configures hd20 mode. register 0x13 [1:0] [00], [01] or [10] interpolation controlconfigur es 1, 2, or 4 interpolation. hd10, mode 7 register 0x01 [7:5] [000] clk_ modeconfigures timing mode. register 0x14 [4] low spifdnhdconfigures hd mode. register 0x14 [2] high spib10n20configures hd10 mode. register 0x13 [1:0] [01] or [10] interpolation controlconfigures 2 or 4 interpolation. optional hd10, mode 8 register 0x01 [7:5] [101] clk_ modeconfigures timing mode. register 0x14 [4] low spifdnhdconfigures hd mode. register 0x14 [2] high spib10n20configures hd10 mode. register 0x13 [1:0] [01] or [10] interpolation controlconfigures 2 or 4 interpolation. clone, mode 10 register 0x01 [7:5] [111] clk_ modeconfigures timing mode. register 0x14 [0] high spic loneconfigures clone mode. register 0x13 [1:0] [01] or [10] interpolation controlconfigures 2 or 4 interpolation.
AD9861 rev. 0 | page 36 of 52 spi register map registers 0x00 to 0x29 of the AD9861 provide flexible operation of the device. the spi allows access to many configurable optio ns. detailed descriptions of the bit functions are found in table 18. table 17. register map reg. name addr 7 6 5 4 3 2 1 0 general 0x00 sdio bidir lsb first soft reset clock mode 0x01 clk_mode[2:0] enable iface2 clkout inv clkout (iface3) power-down 0x02 tx analog txdigital rxdigital pll power- down pll output disconnect rxa power-down 0x03 rx_a analog rx_a dc bias rxb power-down 0x04 rx_b analog rx_b dc bias rx power-down 0x05 rx analog bias rxref diffref vref rx path 0x06 rx_a twos complement rx_a clk duty rx path 0x07 rx_b twos complement rx_b clk duty rx path 0x08 rx ultralow power control rx ultralow power control rx path 0x09 rx ultralow power control rx ultralow power control rx ultralow power control rx path 0x0a rx ultralow power control rx ultralow power control rx ultralow power control tx path 0b dac a offset [9:2] tx path 0c dac a offset [1:0] dac a offset direction tx path 0d dac a coarse gain control dac a fine gain [5:0] tx path 0e dac b offset [9:2] tx path 0f dac b offset [1:0] dac b offset direction tx path 10 dac b coarse gain control dac b fine gain [5:0] tx path 11 txpga gain [7:0] tx path 12 txpga slave enable txpga fast update i/o configuration 13 tx twos complement rx twos complement tx inverse sample interpolation control [1:0] i/o configuration 14 dig loop on spifdnhd spitxnrx spib10n20 spi io control spiclone clock 15 pll bypass adc clock div alt timing mode pll div5 pll multiplier [2:0] clock 16 pll to iface2 pll slow auxiliary converters 17 auxdac a fs [1:0] auxdac b fs [1:0 ] auxdac c fs [1:0] auxadc ref enable auxadc ref fs auxadc 18 start average auxadc a number of auxadc a samples [2:0] auxadc 19 start average auxadc b number of auxadc b samples [2:0] auxadc 1a auxadc a2 [1:0] auxadc 1b auxadc a2 [9:2] auxadc 1c auxadc a1 [1:0] auxadc 1d auxadc a1 [9:2] auxadc 1e auxadc b [1:0] auxadc 1f auxadc b [9:2] auxadc 22 auxspi enable sel 2not1 refsel b start b refsel a select a start a auxadc 23 auxadc clock div[1:0] 24 auxdac a [7:0] 25 auxdac b [7:0] 26 auxdac c [7:0] 28 slave enable upda te c update b update a auxdac 29 auxdac c sync txpwrdwn auxdac b sync txpwrdwn auxdac a sync txpwrdwn power-up c power-up b power-up a
AD9861 rev. 0 | page 37 of 52 table 18. register bit descriptions register bit description register 0: general bit 7: sdio bidir (bidirectional) default setting is low, which indicates that the sp i serial port uses dedicate d input and output lines (4-wire interface), sdio and sdo pins, respectively. se tting this bit high config ures the serial port to use the sdio pin as a bidirectional data pin. bit 6: lsb first default setting is low, which indicates msb fi rst spi port access mode. setting this bit high configures the spi port access to lsb first mode. bit 5: soft reset writing a high to this register resets all the regi sters to their default values and forces the pll to relock to the input clock. the soft reset bit is a one-shot registe r, and is cleared immediately after the register write is completed. register 1: clock mode bits 7C5: clk mode these bits represent the clocking interface for th e various modes. setting 000 is default. setting 111 is used for clone mode. refer to the summary of flexible i/o modes section for definition of clone mode. setting mode 000 standard fd, hd10, hd20 clock (modes 1, 4, 7) 001 optional fd timing (mode 2) 010 not used 011 optional hd20 timing (mode 5) 100 not used 101 optional hd10 timing (mode 8) 110 not used 111 clone mode (mode 10) bit 2: enable iface2 clkout enables the iface2 port to be an output clock. a lso inverts the iface2 output clock in full-duplex mode. bit 1: inv clkout (iface3) inver t the output clock on iface3. register 2: power-down bits 7C5: tx analog (power- down) three options are available to reduce analog powe r consumption for the tx channels. the first two options disable the analog output from tx cha nnel a or b independently, and the third option disables the output of both channels and reduces the power consumption of some of the addi- tional analog support circuitry for maximum power savings. with all three options, the dac bias current is not powered down so recovery times are fa st (typically a few clock cycles). the list below explains the different modes and settings used to configure them. power-down option bits setting [7:5] power-down tx a channel analog output [1 0 0] power-down tx b channel analog output [0 1 0] power-down tx a and tx b analog outputs [1 1 1] bit 4: tx digital (power-down) default setting is low, which enables the transmit path digital to operate as programmed through other registers. by setting this bit high, the digital blocks are not clocked to reduce power consumption. when enabled, th e tx outputs are static, holdin g their last update values. bit 3: rx digital (power-down) setting this bit high powers down the digital section of the receive path of the chip. typically, any unused digital blocks are automatically powered down. bit 2: pll power-down setting this register bit high forces the clkin mu ltiplier to a power-down state. this mode can be used to conserve power or to bypass the inte rnal pll. to operate the AD9861 when the pll is bypassed, an external clock equal to the fast est on-chip clock is supplied to the clkin. bit 1: pll output disconnect setting this register bit high disconnects the pll o utput from the clock path. if the pll is enabled, it locks or stays locked as normal. register 3/4: rx power-down bit 7: rx_a analog/ rx_b analog (power-down) either adc or both adcs can be powered down by setting the appropriate register bit high. the entire analog circuitry of rx ch annel is powered down, including the differential references, input buffer, and the internal digital block. the band gap reference remains active for quick recovery. bit 6: rx_a dc bias/ rx_b dc bias (power-down) setting either of these bits high powers down the input common-mode bias network for the respective channel and requires an input signal to be properly dc-biased. by default, these bits are low, and the rx inputs are self-biased to approx imately avdd/2 and accept an ac-coupled input. register 5: rx power-down bit 7: rx analog bias (power- down) setting this bit high powers down all analog bias ci rcuits related to the rece ive path (including the differential reference buffer). because bias circuits are powered down, an additional power saving, but also a longer recovery time relative to other rx power-down options, will result.
AD9861 rev. 0 | page 38 of 52 register bit description bit 6: rxref (power-down) setting this register bit high powers down inte rnal adc reference circuits. powering down these circuits provides additional power saving over other power-down modes. the rx path wake-up time depends on the recovery of these references typically of the order of a few milliseconds. bit 5: diffref (power-down) setting this bit high powers down the adcs diffe rential references, reft and refb. recovery time depends on the value of the reft and refb decoupling capacitors. bit 4: vref (power-down) setting this register bit high powers down the adc reference circuit, vref. powering down the rx band gap reference allows an external reference to drive the vref pin setting full-scale range of the rx paths. registers 6/7: rx path bit 5: rx_a twos complement/ rx_b twos complement default data format for the rx data is straight binary. setting this bit high generates twos complement data. bit 4: rx_a clk duty/rx_b clk duty setting either of these bits high enables the resp ective channels on-chip duty cycle stabilizer (dcs) circuit to generate the internal clock for the rx bl ock. this option is usef ul for adjusting for high speed input clocks with skewed duty cycle. the dcs mode can be used with adc sampling frequencies over 40 mhz. registers 8/9/a: rx path rx ultralow power control bits set all bits high, in combination with assert ing the adc_lo_pwr pin, to reduce the power consumption of the rx path by a fourth of normal rx path power consumption. registers 0b/0c/0e/0f: tx path dac a/dac b offset these 10-bit, twos complement registers control a dc current offset that is combined with the tx a or tx b output signal. an offset current of up to 12% ioutfs (2.4 ma for a 20 ma full-scale output) can be applied to either differential pin on each channel. the offset current can be used to compensate for offsets that are present in an external mixer stage, reducing lo leakage at its output. the default setting is 0x00, no offset current. the offset cu rrent magnitude is set by using the lower nine bits. setting the msb high adds the offset current to the selected differential pin, while an msb low setting subtracts the offset value. dac a/dac b offset direction this bit determines to which of the differential output pins for the selected channel the offset current is applied. setting this bit low applies the offset to the negative differential pin. setting this bit high applies the offset to the positive differential pin. registers 0d/10: tx path bits 7, 6: dac a/dac b coarse gain control these register bits scale the full-scale output current (ioutfs) of either tx channel independently. iout of the tx channels is a function of the rset resistor, the txpga setting, and the coarse gain control setting. 00 output current scaling by 1/11 01 output current scaling by ? 10 no output current scaling 11 no output current scaling bits 5C0: dac a/dac b fine gain the dac output curve can be adjusted fractionally through the gain tr im control. gain trim of up to 4% can be achieved on each channel individually. the gain trim register bits are a twos complement attention control word. msb, lsb 100000 maximum positive gain adjustment 111111 minimum positive gain adjustment 000000 no adjustment (default) 000001 minimum negative gain adjustment 011111 maximum negative gain adjustment register 11: tx path bits 0C7: txpga gain this 8-bit, straight binary (bit 0 is the lsb, bit 7 is the msb) register controls for the tx programmable gain amplifier (txpga). the txpga provides a 20 db continuous gain range wi th 0.1 db steps (linear in db) simultaneously to both tx channels. by default, this register setting is 0xff. msb, lsb 0000 0000 minimum gain scaling C20 db 1111 1111 maximum gain scaling 0 db register 12: tx path bit 6: txpga slave enable the txpga gain is controlled through register txpga gain setting and, by default, is updated immediately after the register write. if this bit is se t, the txpga gain update is synchronized with the falling edge of a signal applied to the txpwrd wn pin and is enabled during the wake-up from power-down.
AD9861 rev. 0 | page 39 of 52 register bit description bit 4: txpga fast update (mode) the txpga fast bit controls the update speed of the txpga. when fast update mode is enabled, the txpga provides fast gain settling within a few cloc k cycles, which may introd uce spurious signals at the output of the tx path. the de fault setting for this bit is lo w, and the txpga gives a smooth transition between gain settings. fast mode is enabled when this bit is set high. register 13: i/o configuration bit 7: tx twos complement the default data format for tx data is straight binary. set this bit high when providing twos complement tx data. bit 6: rx twos complement the default data format for rx data is straight binary. set this bit high when providing twos complement rx data. bit 5: tx inverse sample by default, the transmit data is sampled on the rising edge of the clkout. setting this bit high changes this, and the transmit data is sampled on the falling edge. bits 1,0: interpolation control these register bits control the interpolation rate of the transmit path. the default settings are both bits low, indicating that both in terpolation filters are bypassed. the msb and lsb are address bits 1 and 0, respectively. setting binary 01 provides an interpolation rate of 2; binary 10 provides an interpolation rate of 4. register 14: i/o configuration bit 5: dig loop on when enabled, this bit enables a digital loop back mode. the digital loop-back mode provides a means of testing digital interfaces and functionali ty at the system level. in digital loop-back mode, the full-duplex interface must be enabled. (r efer to the flexible i/o interface options section.) the device accepts digital input from the bus accordin g to the fd mode timing and uses the tx digital path (with enabled interpolation and other digital settings); the processed da ta is then output from the rx path bus. bit 4: spi_fdnhd control bit to configure full-duplex (high) or ha lf-duplex (low) interface mode. this register, in combination with the spib10n20 register, configures the interface mode of fd, hd10, or hd20. the register setting is ignored for clone mode operation . by default, this regist er is set high, and the device is in fd mode. bit 3: spitxnrx control bit used for toggling betw een transmit or receive mode for the half-duplex clock modes. high represents tx and low represents rx. bit 2: spib10n20 control bit for 10-bit or 20-bit modes. high represents 10-bit mode and low represents 20-bit mode. bit 1: spi io control use in conjunctio n with spitxnrx [register14, bit 3] to override external txnrx pin operation. bit 0: spiclone set high when in clone mode (see the flexible i/o interface options section for definition of clone mode). clk_mode should also be set to binary 111, i.e., [register 01[7:5] = 111. register 15: clock bit 7: pll_bypass setting this bit high bypasses the pll. when bypassed, the pll remains active. bits 5: adc clock div by default, the adcs are driven directly from clkin in normal timing operation or from the pll output clock in the alternative timing operation. this bit is used to divide the source of the adc clock prior to the adcs. the default setting is low and performs no division. setting this bit high divides the clock by 2. bit 4: alt timing mode the timing table in the data sheet describes two timing modes: the normal timing operation mode and the alternative timing operation mode. the default configuration is normal timing mode and the clkin drives the rx path. in alternative timi ng mode, the pll output is used to drive the rx path. the alternative operation mode is configured by setting this bit high. bit 3: pll div5 the output of the pll can be divided by 5 by setting this bit high. by default, the pll directly drives the tx digital path with no division of its output. bits 2C0: pll multiplier these bits control the pll multiplication factor. a de fault setting is binary 000, which configures the pll to 1 multiplication factor. th is register, in combination with the pll div5 register, sets the pll output frequency. the programmabl e multiplication factors are 000 1 001 2 010 4 011 8 100 16 101 C 111 not used register 16: clock bit 5: pll to iface2 setting this bit high switches the iface2 output sign al to the pll output clock. it is valid only if register 0x01, bit 2 is enabled or if full-duplex mode is configured. bit 2: pll slow changes the pll loop bandwidth and changes the profile of the phase noise generated from the pll clock.
AD9861 rev. 0 | page 40 of 52 register bit description register 17: auxiliary converters bits 7C2: auxdac a fs/auxdac b fs/auxdac c fs these register bits independently scale the full- scale output voltage for the auxdacs. if the full- scale voltage is programmed to a value greate r than pll_vdd C 0.2 v, the auxdac becomes nonlinear in this region. msb, lsb auxdac full-scale output voltage 00 3.0 v 01 3.3 v 10 2.5 v 11 2.7 v bit 1: auxadc ref enable this bit enables the on-chip, supply independent reference for the auxadc. by default, the auxadc uses the pll_avdd supply for it s full-scale voltage level. bit 0: auxadc ref fs when the auxadc ref enable bit is set high, this bi t allows the user to select the full-scale value of the auxadc. a low setting sets the full-scale value to 3.0 v; a high setting sets the full-scale value to 2.5 v. if the full-scale voltage is programmed to a value greater than pll_vdd C 0.2 v, the auxadc is not linear in this region. registers 18/19 : auxadc bit 7: start average auxadc a/ start average auxadc b these registers are used to initiate a conversion cycle of the auxadcs for a number of consecutive samples and then report the average result. the number of consecutive samples is programmed in the number of auxadc a/auxadcb samples register. the external pin aux_spi_cs can be config- ured to allow it to initiate the start average conver sion cycle. the result is placed in the appropriate register corresponding to the auxadc output [registers 0x1a to 0x21]. bit 7: number of auxadc a/ auxadc b samples these bits control the number of samples that the auxadc collects and uses to calculate an average value. this register is used in conj unction with the start average auxadc register. msb, lsb number of samples to average 000 1 001 2 010 4 011 8 100 16 101 32 110 64 111 not used registers 1aC21: auxadc these 10-bit, offset binary registers are read-onl y and store the last corresponding auxadc output values. the AD9861 has two auxadc sar converters : auxadc a and auxadc b. auxadc a has a multiplexed input, which allows the user to select either input by using the select a register. the 10 bits are broken into two registers, one containing the upper eight bits and the other containing the lower two bits. register 22: auxadc bit 7: auxspi (enable) enables the auxspi , which can be used to initiate a conver sion and read back one of the auxadcs. bit 6: sel 2not1 if the auxiliary serial port is used, this bit select s which auxadc, 1 or 2, uses the dedicated auxiliary serial port. by default (low setting ), the auxiliary serial port controls auxadc a. setting this bit high allows the auxiliary serial port to control auxadc b. bits 5, 2: refsel b/a by default, the auxadcs use an external reference applied to the aux_ref pin. this voltage acts as the full-scale reference for the selected auxadc. either auxadc can use an internally generated reference, which can be a buffere d version of the analog supply voltage or a supply independent, 3.0 v or 2.5 v internal reference. to enable use of the internal reference for either of the auxadcs, set the respective refsel register high. for internal reference configuration, see register 17. bit 1: select a this bit is used to select which of the two inputs is connected to the auxadc. by default (setting low), the aux_adc_a2 (aux2 pin) is connected to auxadc a. setting the respective bit high connects the aux_adc_a1 (aux1 pin) to auxadc a. bit 3, 0: start b/a setting either of these bits to high initiates a conversion of the respective auxadc, a or b. the register bit always reads back a low.
AD9861 rev. 0 | page 41 of 52 register bit description register 23: auxadc bits 1,0: auxadc clock div the auxadcs clock can be based on either the clock driving the rx adc, or it can be driven from the spi_clk. the conversion rate of the auxadcs shou ld be less than 40 mhz. in order to facilitate a slower speed clock for the auxadc, these bits are us ed to divide down the rx adc clock prior to driving the auxadc. the following options are programmable through this register: msb, lsb auxadc sampling rate 00 rx adc clock/4 01 rx adc clock/2 10 rx adc clock 11 spi_clk drives auxadc registers 24, 25, 26: auxdac auxdac a, b, and c output control word three 8-bit, straight binary words are used to control the output of three on-chip auxdacs. the auxdac output changes take effe ct immediately after any of the se rial writes are completed. the dac output control words have de fault values of 0. the sma ller programmed output controlled words correspond to lower dac output levels. register 28: auxdac bit 7: slave enable a low setting (default) updates the auxdacs afte r the respective register is written to. to synchronize the auxdac outputs to each other, a slave mode can be enabled by setting this bit high and then setting the appr opriate update registers high. bits 2/1/0: update c, b, and a setting a high bit to any of these bits initiates an update of the respective auxdac, a, b or c, when slave mode is enabled using the slave enable register. the register bit is a one-shot and always reads back a low. be sure to keep the slave enable bit high when using the auxdac synchronization option. register 29: auxdac bits 7/6/5: auxdac c/b/a sync txpwrdwn setting any of these bits high synchronizes auxd ac updates only when the txpwrdwn rising edge occurs. this syncronizes the auxdac update to the tx path power-up. bits 2/1/0: power up c, b, and a setting any of these bits high powers up the appr opriate auxdac. by default, these bits are low and the auxdacs are disabled.
AD9861 rev. 0 | page 42 of 52 programmable registers the AD9861 contains internal registers that are used to configure the device. a serial port interface provides read/write access to the internal registers. single-byte or dual-byte transfers are supported as well as msb first or lsb first transfer formats. the AD9861s serial interface port can be configured as a single pin i/o (sdio) or as two unidirectional pins for in/out (sdio/sdo). the serial port is a flexible, serial communications port, allowing easy interface to many industry-standard microcontrollers and microprocessors. general operation of the serial interface by default, the serial port accepts data in msb first mode and uses four pins: sen, sclk, sdio, and sdo by default. sen is a serial clock enable pin; sclk is the serial clock pin; sdio is a bidirectional data line; and sdo is a serial output pin. sen is an active low control gating read and write cycles. when sen is high, sdo and sdio go into a high impedance state. sclk is used to synchronize spi read and writes at a maximum bit rate of 30 mhz. input data is registered on the rising edge, and output data transitions are registered on the falling edge. during write operations, the registers are updated after the 16th rising clock edge (and 24th rising clock edge for the dual-byte case). incomplete write operations are ignored. sdio is an input data only pin by default. optionally, a 3-pin interface may be configured using the sdio for both input and output operations and three-stating the sdo pin. refer to the sdio bidir bit in register 0x00 (table 18). sdo is a serial output data pin used for readback operations in 4-wire mode and is three-stated when sdio is configured for bidirectional operation. there are two phases to a communication cycle with the AD9861. phase 1 is the instruction cycle, which is the writing of an instruction byte into the AD9861, coincident with the first eight sclk rising edges. the instruction byte provides the AD9861 serial port controller with information regarding the data transfer cycle, which is phase 2 of the communication cycle. the phase 1 instruction byte defines whether the upcoming data transfer is read or write, the number of bytes in the data transfer (one or two), and the starting register address for the first byte of the data transfer. the first eight sclk rising edges of each communication cycle are used to write the instruction byte into the AD9861. the remaining sclk edges are for phase 2 of the communication cycle. phase 2 is the actual data transfer between the AD9861 and the system controller. phase 2 of the communication cycle is a transfer of one or two data bytes as determined by the instruction byte. normally, using one communication cycle in a multibyte transfer is the preferred method; however, single byte communication cycles are useful to reduce cpu overhead when register access requires only one byte. an example of this is to write the AD9861 power-down bits. all data input to the AD9861 is registered on the rising edge of sclk. all data is driven out of the AD9861 on the falling edge of sclk. instruction byte the instruction byte contains the information shown in table 19, and the bits are described in detail after the table. table 19. instruction byte msb d6 d5 d4 d3 d2 d1 lsb r/nw 2/n1 byte a5 a4 a3 a2 a1 a0 r/nw bit 7 of the instruction byte determines whether a read or write data transfer will occur after the instruction byte write. logic high indicates a read op eration. logic low indicates a write operation. 2/n1 byte bit 6 of the instruction byte determines the number of bytes to be transferred during the data transfer cycle of the communication cycle. logic high indicates a 2-byte transfer. logic low indicates a 1-byte transfer. a5, a4, a3, a2, a1, a0 bits 5, 4, 3, 2, 1, and 0 of the instruction byte determine which register is accessed during the data transfer portion of the communication cycle. for 2-byte transfers, this address is the starting byte address. the second byte address is automatically decr emented when the interface is configured for msb first transfers. for lsb first transfers, the address of the second byte is automatically incremented. table 20. serial port interface timing maximum sclk frequency (f sclk ) 40 mhz minimum sclk high pulse width (t pwh ) 12.5 ns minimum sclk low pulse width (t pwl ) 12.5 ns maximum clock rise/fall time 1 ms data to sclk timing (t ds ) 12.5 ns data hold time (t dh ) 0 ns
AD9861 rev. 0 | page 43 of 52 write operations the s p i wr i te op era t ion us es t h e in s t r u c t io n h e ader t o co nf ig- ur e a 1-b y t e o r 2-b y t e r e g i s ter wr i t e usin g t h e 2/n1 b y t e s e t t ing. the ins t r u c t io n b y t e fol l o w e d b y t h e r e g i s t er da t a is wr i t t e n s e r i al l y in t o t h e de vice thr o u g h th e s d i o p i n o n r i sin g edg e s o f t h e i n t e r f ace clo c k, sclk. the da t a can b e t r a n s f er r e d ms b f i rs t o r ls b f i rs t dep e ndin g on t h e s e t t i n g o f t h e l s b f i rs t r e g i s t er b i t. the wr i t e o p era t io n is t h e s a m e r e ga r d les s o f s d i o b i dir re g i ste r s e tt i n g . f i gur e 78 t o f i gur e 80 a r e exa m ples o f wr i t in g da t a in t o t h e de vice . f i gur e 7 8 s h o w s a 1 - b y te wr i te wi t h msb f i rs t; f i gur e 79 show s a 2 - by te w r ite w i t h m s b f i r s t ; an d f i g u re 8 0 show s a 2-b y t e wr i t e w i t h ls b f i rs t. n o te t h e dif f er en ce s b e tw e e n ls b a nd ms b f i rst m o de s: b o t h t h e in st r u c t io n h e a d er a nd da t a a r e r e v e rs e d , and t h e s e con d da t a b y t e r e g i s t er lo c a t i o n is dif f er en t. i n t h e def a u l t m s b f i rs t mo de , t h e s e con d da t a b y t e is wr i t t e n to a de cr e m en t e d r e g i s t er addr es s. i n ls b f i rs t mo de , t h e s e con d da t a b y te is wr i t t e n t o an i n cr e m e n t e d r e g i s ter addr es s. instruction header register data t s t ds t dh t hi t lo t clk t h don't care don't care 2/1 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 don't care don't care sen s cl k sdio r/w 03606-0-022 f i gure 78. 1-b y te s e ri al r e gis t er w r ite in msb f i rs t mode t h t s t ds t dh t hi t lo t clk sen s cl k sdio 03606-0-023 don't care don't care a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 r/w 2/1 don't care don't care instruction header (register n) register (n) data register (n? 1) data f i gure 79. 2-b y te s e ri al r e gis t er w r ite in msb f i rs t mode t h t s t ds t dh t hi t lo t clk sen s cl k sdio 03606-0-024 don't care don't care don't care don't care instruction header (register n) register (n) data register (n+1) data a0 a1 a2 a3 a4 a5 d0 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 r/w 2/1 f i gure 80. 2-b y te s e ri al r e gis t er w r ite in lsb f i rs t mode
AD9861 rev. 0 | page 44 of 52 read op eration t h e re a d b a ck of re g i ste r s c a n b e a s i ng l e or du a l d a t a by t e o p er a t ion. t h e re ad b a ck c a n b e co nf igur e d to us e 3- wir e o r 4-w i r e an d ca n b e fo r m a t te d wi t h ms b f i rst o r ls b f i rst. t h e in st r u c t io n h e a d er is wr i t t e n t o t h e d e vice e i t h e r ms b o r ls b f i rs t (dep e n di n g o n t h e m o de) fol l o w e d b y t h e 8-b i t o u t p u t da t a ( a ppropr i a tely m s b or l s b ju st i f i e d ) . by d e f a u l t , t h e output d a t a is s e n t to t h e de dic a te d o u t p u t p i n ( s d o ) . thre e- wir e o p er a t i o n ca n be co nf igur ed b y s e t t in g t h e s d i o b i dir r e g i s t er . i n 3-wir e mo d e , t h e sdio pi n b e c o me s a n output pi n af te r re c e iv i n g t h e 8-b i t ins t r u c t io n he ader wi t h a r e ad b a ck r e q u est. f i g u re 8 1 show s a 4 - w i re spi re a d w i t h m s b f i r s t ; f i g u re 8 2 show s a 3 - w i re re a d w i t h m s b f i r s t ; an d f i g u re 8 3 show s a 4 - w i re re a d w i t h l s b f i r s t . t h t s t ds t dh t hi t lo t clk t dv sen s cl k sdio sdo 03606-0-025 don't care don't care don't care don't care don't care don't care instruction header output register data a5 d7 d6 d5 d4 d3 d2 d1 d0 a4 a3 a2 a1 a0 r/w 2/1 f i gure 81. 1-b y te s e ri al r e gis t er r e ad back in msb f i rs t m o de , sdio bid i r bit s e t l o gic l o w (d efault, 4- w i r e m o de) sen s cl k sdio 03606-0-026 don't care don't care don't care a5 a4 a3 a2 a1 a0 r/w 2/1 don't care d7 d6 d5 d4 d3 d2 d1 d0 t s t ds t dh t hi t lo t clk t dv t h output register data instruction header f i gure 82. 1-b y te s e ri al r e gis t er r e ad back in msb f i rs t mode , sdio bid i r bit s e t l o gic high ( d efault, 3- w i r e m o de) sen s cl k sdio sdo 03606-0-027 don't care don't care don't care a0 a1 a2 a3 a4 a5 r/w 2/1 don't care don't care don't care d0 d1 d2 d3 d4 d5 d6 d7 t s t ds t dh t hi t lo t clk t dv t h output register data instruction header f i gure 83. 1-b y te s e ri al r e gis t er r e ad back in lsb f i rs t mode , sdio bid i r bit s e t l o gic l o w (d efault, 4- w i r e m o de)
AD9861 rev. 0 | page 45 of 52 clock distribution block theory/description the AD9861 uses a clock distribution block to distribute the timing derived from the input clock (applied to the clkin pin, referred to here as clkin) to the rx and tx paths. there are many options for configuring the clock distribution block, which are available through internal register settings. the clock distribution block diagram section describes the timing block diagram breakdown, followed by the data timing for the different data interface options. the clock distribution block contains a pll, which includes an optional output divide-by-5 circuit, an adc divide-by-2 circuit, multiplexers, and other digital logic. there are two main methods of configuring the rx path timing of the AD9861, normal timing mode and alternative timing mode, which are controlled through register alt timing mode [register 0x15, bit 4]. in normal timing mode, the rx path clock is driven directly from the clkin input and the tx path is driven by a clock derived from clkin multiplied by the on chip pll. in alternative timing mode, the input clock is applied to the pll circuitry, and the pll output clock drives both the rx path clock and tx path clock. because alternative timing mode uses the pll to derive the rx path clock, the adc performance may degrade slightly. this degradation is due to the phase noise from the pll. typically it occurs in undersampling applications when the input signal is above the first nyquist zone of the adc. the pll can provide 1, 2, 4, 8, and 16 multiplication or can be bypassed and powered down through register pll bypass [register 0x15, bit 7] and through register pll power- down [register 0x2, bit 2]. the pll requires a minimum input clock frequency of 16 mhz and needs to provide a minimum pll output clock of 32 mhz. this limit applies to the pll output prior to the optional divide-by-5 circuitry. for clock frequencies below these limits, the pll must be bypassed. the pll maximum output frequency before the divide-by-5 cir- cuitry is 350 mhz. table 21 shows the input and output clock rates for all the multiplication settings. table 21. pll input and output minimum and maximum clock rates pll setting input clock (min/max) (mhz) output clock (min/max) (mhz) 1 (pll bypassed) 1/200 1/200 1 (pll enabled) 32/200 32/200 2 16/100 32/200 4 16/50 64/200 8 16/25 128/200 * 1/5 32/200 6.4/40 * 2/5 16/175 6.4/70 * 4/5 16/87.5 12.8/70 * 8/5 16/43.75 25.6/70 * 16/5 16/21.875 51.2/70 * indicates pll output divide-by-5 circuit enabled. clock distribution block diagram the clock distribution block diagram is shown in figure 84. an output clock formatter configures the output synchronization signals, iface1, iface2, and iface3. these interface pin signals depend on clock mode setting, data i/o configuration, and other operational settings. clock mode and data i/o configuration are defined in register settings of clk_mode, spifdnhd, and spib10n20. table 22 shows the configuration of the iface1, iface2 and iface3 pins relative to clock mode (for half-duplex cases, the iface1 pin is an input that identifies if the device is in rx or tx operation mode). the clock mode is used to specify the timing for each data interface operation modes, which are discussed in detail in the flexible i/o interface options section. the t and r extensions after the half-duplex modes 4, 5, 7, 8, and 10 in the table 22 indicate that the device is in transmit or receive operation mode. the default clock mode setting [register 0x01, bits 5C7, clk_mode] of 000 configures clock mode 1 for the full-duplex operation, mode 4 for half-duplex 20 operation and mode 7 for half-duplex 10 operation. modes 2, 5, 8, and 10 are optional timing configurations for the AD9861 that can be programmed through register 0x01 clk_mode.
AD9861 rev. 0 | page 46 of 52 03606-0-067 rx digital block rx path tx digital block tx path iface2 iface3 output clock formatter clkin 1 2 4 5 6 80mhz max 1, 2 1, 2, 4, 8, 16 1, 5 1. alternate timing mode: reg 0x15, bit 4 2. pll multiplication setting: reg 0x15, bits 2 ? 0 3. pll output divide by 5; reg 0x15, bit 3 4. rx path divide by 2: reg 0x15, bit 5 5. pll bypass path: reg 0x15, bit 7 6. interp control, tx/rx inv iface3, clk mode, inv iface2, fd/hd, 10/20 3 f i gure 84. cl ock d i s t ributi on b l o c k d i a g r a m table 22. i n terface pin s (iface1, iface2, iface3) con f iguration definition for flexible in terface operation clock mode 1 2 4 t 4 r 5 t 5 r 7 t 7 r 8 t 8 r 1 0 t 1 0 r pin full-duplex half-duplex, 20- bit half-duplex, 10- bit clone m o d e i f a c e 1 t x s y n c tx / rx tx / rx tx / rx i f a c e 2 b u f f _ c l k i n r x s y n c optional clko u t optiona l clkou t optiona l clkou t i f a c e 3 t x c l o c k tx clock rx clock tx clock rx clock tx clock rx clock tx clock rx clock tx clock rx clock the tx clo c k out p u t f r e q ue n c y dep e n d s on w h et h e r t h e da t a is i n i n te rl e a ve d or p a r a l l el ( n oni n te rl e a ve d) c o n f i g u r a t i o n. m o d e s 1, 2, 7, 8, a n d 10 us e tx in t e rlea ved da ta and r e q u ir e ei t h er 2 o r 4 in t e r p ol a t ion t o b e ena b le d . ? d a c u p da t e r a te = clki n pll s e t t ing. ? n o n i n t e r l e a v ed t x d a ta c l oc k fr e q u e n c y = c l k i n p l l se t t in g 1/ (in t er po la ti o n ra t e ). ? i n t e r l e a v e d t x da ta c l o c k f r eq uen c y = 2 clkin p ll se t t in g 1/ (in t er po la ti o n ra t e ). the rx clo c k do es n o t dep e nd o n w h et h e r t h e da t a is in ter- le a v e d o r p a r a l l el, b u t do es de p e nd o n t h e conf igur a t io n o f t h e t i min g mo de: no r m a l o r a l ter n a t ive. ? n o rm al ti m i n g m o de , r x c l oc k f r eq ue n c y = c l k i n a d c di v fac t o r (if ena b le d). ? a l ter n a t ive t i mi n g mo de, rx clo c k f r e q uen c y = clki n p ll s e t t in g a d c di v f a c t o r (if ena b le d). an o p tio n al clk o ut f r o m if a c e2 is a v a i la ble as a s t ab le sys t em clo c k r u nnin g a t t h e c l kin f r e q ue n c y o r t h e tx d a c u p d a te ra te , w h i c h is e q u a l t o c l kin pll s e t t in g. s e t t in g t h e ena b le if a c e2 r e g i s t er [reg ist e r 0x01, b i t 2] en a b les t h e if a c e2 o p tio n al c l o c k o u t p u t . i n fd m o de , the if a c e2 p i n a l wa y s ac ts as a clo c k o u tp u t ; t h e ena b le if a c e 2 p i n c a n b e us ed t o in v e r t th e if a c e2 o u t p u t . c o nfigur ation the AD9861 timin g f o r th e tran smi t p a th and f o r th e r e cei v e p a t h de p e n d on t h e m o d e s e t t ing a nd va r i o u s p r o g r a mma b l e opt i ons . t h e re g i ste r s t h a t af f e c t t h e output cl o c k t i m i ng a n d da ta in p u t/o u t p u t timin g a r e c l k_m o de [2:0]; ena b le if a c e2; in v cl k o ut (if a ce3); tx in v e rs e s a m p le; i n t e r p ola t ion co n t r o l; p l l by p a s s ; a d c c l o c k d i v ; a l t t i m i n g m o d e ; p l l d i v 5 ; p l l m u l t i p li ca t i o n ; a nd pll to if a c e2. the cl k_ mo de r e g i ster is dis c us s e d p r e v i o us ly . t a b l e 23 sh o w s t h e o t h e r r e g i s t er b i ts t h a t a r e us e d t o co nf igur e t h e o u t p ut clo c k t i mi n g and da t a l a t c hin g o p tio n s a v a i l a b l e in t h e ad986 1.
AD9861 rev. 0 | page 47 of 52 table 23. serial registers related to the clock distrib u tion block register name register addre ss, bit(s) function enable iface2 register 0x01, bit 2 0: there is no clock output from iface2 pin, except in fd mode. 1: the iface2 pi n outputs a continuous refe rence clock from the pll outpu t . in fd mode, this inverts the iface2 output. inv clkout (iface3) register 0x01, bit 1 0: the iface3 cl ock output is not inverted. 1: the iface3 cl ock output is inverted. tx inverse sample register 0x13, bit 5 0: the tx path d a ta is latched relative to the out p ut tx clock rising edge. 1: the tx path d a ta is latched relative to the out p ut tx clock falling edge. interpolation control register 0x13, bit 1:0 sets interpolati o n of 1, 2, or 4 for the t x path. pll bypass register 0x15, bit 7 0: the pll bloc k is used to generate system clock. 1: the pll block is bypassed to generate system clock. adc clock div register 0x15, bit 5 0: adc clock rat e eq uals the rx path freq uency. 1: adc clock is one-half the rx path freq uency. alt timing mode register 0x15, bit 4 0: clki n is used to drive the rx path clock. 1: pll block output is used to dr ive the rx path clock. pll div5 register 0x15, bit 3 0: pll bl ock output clock is not divided down. 1: pll block output clock is divided by 5. pll m u ltiplier register 0x15, bit 2:0 s e t s m u l t i p l i c a t i o n f a c t o r o f t h e p l l b l o c k t o 1 ( 0 0 0 ) , 2 ( 0 0 1 ) , 4 ( 0 1 0 ) , 8 ( 0 1 1 ) , o r 16 x ( 1 00 ). pll to ifac e2 register 0x16, bit 5 0: if enable ifac e2 register is set, iface2 outpu t s buffered clki n. 1: if enable iface2 register is set, iface2 outpu t s buffered pll o utput clock. t r a n smi t ( t x) t i min g r e q u ir es sp e c if ic s e t u p and h o l d t i m e s t o p r o p erly la t c h da t a t h r o u g h t h e da t a in ter face b u s. th es e t i ming p a ra m eters a r e s p e c if ie d r e l a t i ve t o a n i n t e r n al ly g e n e ra t e d o u t p u t r e f e r e n c e c l o c k. th e AD9861 has tw o in t e r f ace c l o c ks p r o v ided thr o u g h the if a c e3 a nd if a c e2 p i ns. th e tran smi t t i min g sp e c if ica t io n s , s e t u p an d h o ld t i me , p r o v ide a mini m u m re qu i r e d w i nd o w of v a l i d d a t a . se t u p ti m e ( t set u p ) is t h e t i me r e q u ir e d fo r d a t a t o ini t ia l l y s e t t l e t o a valid log i c lev e l p r io r t o the r e la t i v e o u t p u t timin g edg e . ho l d t i m e ( t ho l d ) is t h e t i m e a f ter t h e o u t p u t t i min g e d g e t h a t v a li d d a ta m u s t r e m a i n o n th e da ta b u s t o be p r o p e r l y la t c h e d . f i gur e 85 s h o w s t setu p a nd t ho l d r e la t i v e t o if a c e3 fal l in g edg e . n o t e tha t in so m e ca se s n e g a t i v e tim e i s s p eci f i e d , f o r e x a m p l e wi t h t ho l d ti mi n g , wh i c h m e a n s th a t t h e h o ld tim e e d g e occur s b e f ore t h e rel a t i ve output cl o c k e d ge. iface3 (clkout) tx data 03606-0-028 t setup t hold f i gu r e 8 5 . t x da ta t i m i n g dia g r a m t a b l e 24 sh o w s typ i cal s e t u p-and-h o ld tim e s f o r th e AD9861 in t h e va r i o u s m o de co nf igur a t ion s . table 24. a d 9 861 typical tx data latch timing r e lative t o iface3 falling edge mode no. mode name t set u p (ns) t hold (ns) 1 f d 5 C 2 . 5 2 optional fd 5 C2.5 4 hd20 5 C1.5 5 optional hd20 5 C1.5 7 h d 1 0 5 C 2 . 5 8 optional hd10 5 C2.5 10 clone 5 C1.5 r e c e ive ( r x ) p a t h d a t a i s output af te r a re f e re n c e output cl o c k e d ge. t h e t i me d e l a y of t h e r x d a t a re l a t i ve to a re f e re nc e output c l o c k is cal l ed t h e o u t p u t dela y , t od . the ad986 1 has tw o p o ss ibl e i n te r f a c e cl o c k s prov i d e d t h rou g h t h e i f a c e 3 and if a c e2 p i n s . f i gur e 86 s h o w s t od r e la t i v e t o if a c e3 r i sin g ed g e . n o t e tha t i n so m e ca se s n e g a ti v e tim e i s s p eci f i e d , wh i c h m e a n s th a t th e o u t p u t da t a tra n s i ti o n occur s p r i o r t o th e r e la ti v e output cl o c k e d ge. iface3 (clkout) rx data 03606-0-029 t od f i g u re 86. r x d a t a ti ming d i ag r a m
AD9861 rev. 0 | page 48 of 52 table 25 shows typical output delay times for the AD9861 in the various mode configurations. table 25. AD9861 rx data latch timing mode no. mode name t od data delay [ns] relative to: 1 fd +2.5 ns relative to iface2 rising edge +1 ns relative to iface3 rising edge 2 optional fd +1 ns relative to iface3 rising edge +2 ns iface2 (rxsync) relative to lsb 4 hd20 ?1.5 ns relative to iface3 rising edge 5 optional hd20 ?0.5 ns relative to iface3 rising edge 7 hd10 ?1.5 ns relative to iface3 rising edge 8 optional hd10 +0.5 ns relative to iface3 rising edge +0 ns u12 (rxsync) relative to lsb 10 clone +1.5 ns relative to iface3 rising edge configuration without serial port interface (using mode pins) the AD9861 can be configured using mode pins if a serial port interface is not available. this section applies only to configu ring the AD9861 without an spi. refer is the digital block, configuring with mode pins section for further information. when using the mode pin option, the pins shown in table 26 are used to configured the AD9861. table 26. using mode pin (spi disabled) to config ure timing (spi_cs, pin 64, must be tied low) clock mode interpolation setting pll setting fd/ hd pin 3 10/ 20 pin 17 interp1,interp0 pin 1, pin 2 mode 1 (fd) 2 4 2 4 1 n/a 1 0, 1 1, 0 mode 4 (hd20) 1 2 4 bypassed 2 4 0 0 0, 0 0, 1 1, 0 mode 7 (hd10) 2 4 2 4 0 1 0, 1 1, 0 1 pin 17 (iface2) is an output clock in fd mode.
AD9861 rev. 0 | page 49 of 52 outline dimensions 1 64 16 17 49 48 32 33 0.45 0.40 0.35 0.60 max 0.60 max 0 . 2 5 mi n 0.50 bsc 0. 2 0 r e f * compliant to jedec standards mo-220-vmmd except for exposed pad dimension bottom view 0.30 0.25 0.18 7. 50 re f 7.25 7.10 sq* 6.95 12 max 0.80 max 0.65 typ 1.00 0.85 0.80 0.05 max 0.02 nom seating plane top view 9.00 bsc sq 8.75 bsc sq pin 1 indicator pin 1 indicator f i gure 87. 6 4 -l ead l e ad f r a m e ch ip s c a l e p a ck ag e (lfcs p ) [cp - 6 4 ]
AD9861 rev. 0 | page 50 of 52 ordering guide model temperature range package description package option AD9861bcp-50 C40 c to +85 c (ambient) 64-lead lfcsp cp-64 AD9861bcp-80 C40 c to +85 c (ambient) 64-lead lfcsp cp-64 AD9861bcprl-50 C40 c to +85 c (ambient) 64-lead lfcsp cp-64 AD9861bcprl-80 C40 c to +85 c (ambient) 64-lead lfcsp cp-64 AD9861-50eb 25c (ambient) evaluation board AD9861-80eb 25c (ambient) evaluation board
AD9861 rev. 0 | page 51 of 52 notes
AD9861 rev. 0 | page 52 of 52 notes ? 2003 analo g de vices, inc. all rights reserve d . tra d em arks and registered tra d ema r ks are the prop erty of their respective owners . c03606C0 C 11/03(0)

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